Bulletin of the American Physical Society
APS March Meeting 2019
Volume 64, Number 2
Monday–Friday, March 4–8, 2019; Boston, Massachusetts
Session S35: 3D Integration for Superconducting QubitsFocus
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Sponsoring Units: DQI Chair: Markus Brink Room: BCEC 205B |
Thursday, March 7, 2019 11:15AM - 11:51AM |
S35.00001: Multilayer coaxial superconducting circuits with integrated 3D wiring Invited Speaker: Peter Leek Superconducting circuits are one of the leading candidates for the realization of quantum computers, in particular for near-term applications which may already be reached with circuits consisting of a few hundred qubits, provided they are operated at high fidelity. Until recently, the topology of superconducting circuits has typically been constrained to two dimensions, which becomes increasingly difficult as the number of qubits is scaled up and control and measurement wiring is needed for qubits in the middle of large arrays. It is natural to explore new circuit topologies that incorporate wiring in the third dimension to solve this problem. In this talk I will present an overview of an approach that builds on a coaxially-symmetric circuit QED unit cell with out-of-plane wiring [1] that provides a simple route to scaling to grids of many qubits. In this approach, arrays of qubits and resonators can be fabricated on opposing sides of a substrate and capacitively coupled, while control and readout are achieved via off-chip coaxial wires which run perpendicular to the chip plane and are built into a precision micromachined enclosure that provides a high-quality microwave environment for the circuit. |
Thursday, March 7, 2019 11:51AM - 12:03PM |
S35.00002: Flux Tunable Superconductings Qubits With 3D Wiring Jeremy Bejanin, Carolyn Earnest, Thomas G McConkey, Evan Peters, Matteo Mariantoni Superconducting qubits have the potential to lead to large-scale quantum computers, where 10^5 or more qubits are arranged in two-dimensional arrays forming quantum processing units (QPUs) on silicon chips. Operating such an array necessarily requires control signals to come from wires in the third dimension, so as to avoid overlapping control lines on the device itself. While various implementations of 3D wiring have been realized in the last few years, none has been used with flux-tunable superconducting qubits, which require a current line to inductively bias the superconducting loop of a SQUID. In this talk, we show and characterize the performance of tunable superconducting Xmon transmon qubits using the quantum socket, for which the control wiring is fully 3D, including the fast flux bias lines used for frequency tuning. We demonstrate one-qubit gates and perform quantum gate tomography to quantify gate fidelity as a function of flux bias for two Xmon transmon qubits. |
Thursday, March 7, 2019 12:03PM - 12:15PM |
S35.00003: Increasing reliability for 3D integrated high-coherence superconducting qubits Bethany M Niedzielski, David K Kim, Jonilyn L Yoder, Danna Rosenberg, Mollie E. Schwartz, Rabindra Das, Alexander Melville, Donna-Ruth Yost, Justin Mallek, Alexandra L Day, Steven Weber, Cyrus F. Hirjibehedin, William D Oliver As designs for superconducting qubits become more complex, 3D integration of two or more vertically bonded chips can enable increased density and connectivity. Precise control of the spacing between these chips is required to give designers accurate parameters to plan and predict circuit performance. In this talk, we will describe our process for using silicon hard-stop mesas to control chip spacing and tilt, and our integration of these features with our high-coherence superconducting qubit fabrication process. |
Thursday, March 7, 2019 12:15PM - 12:27PM |
S35.00004: 3D-wired coaxial circuit QED I: Extension to multi-qubit devices Salha Jebari, Joseph Rahamim, Andrew D Patterson, Peter A Spring, Takahiro Tsunoda, Sophia Sosnina, Martina Esposito, Kitti Ratter, Giovanna Tancredi, Brian Vlastakis, Peter Leek In order to realise superconducting circuits at a sufficient scale for useful near-term applications, an architecture is required which implements good connectivity between qubits, and allows for selective readout and control of the qubits without introducing detrimental crosstalk or decoherence. Since the number of readout and control lines increases linearly with the number of qubits, scaling up a circuit which is constrained to a 2D surface becomes increasingly difficult. Here we present the extension of our recently demonstrated 3D-wired coaxial circuit QED architecture [1] to 2D arrays of qubits. Qubits and readout LC resonators are fabricated on opposing sides of a substrate and entirely off-chip coaxial wiring is built into the chip enclosure and runs perpendicular to the chip plane. Scaling is simply achieved by the repetition of the unit cell across a 2D plane. We present the performance of multi-qubit circuits based on this architecture, including coherence times and two-qubit gate fidelities. |
Thursday, March 7, 2019 12:27PM - 12:39PM |
S35.00005: 3D-wired coaxial circuit QED II: Evaluation of crosstalk Joseph Rahamim, Salha Jebari, Andrew D Patterson, Peter A Spring, Takahiro Tsunoda, Sophia Sosnina, Martina Esposito, Kitti Ratter, Giovanna Tancredi, Brian Vlastakis, Peter Leek Evaluating crosstalk in multi-qubit superconducting circuits is becoming increasingly important. Control-wiring crosstalk can cause coherent control errors that become increasingly impractical to correct in larger scale circuits, and measurement crosstalk can induce dephasing. Selective control and coupling is intrinsic to our architecture [1] due to the use of coaxial circuit elements on two planes, mode-matched to out-of-plane 3D wiring. However, in any multi-qubit circuit the electromagnetic fields associated with individual circuit elements and control signals will never be perfectly confined. We present a careful characterisation of resonator and qubit control-line crosstalk, as well as measurement crosstalk due to coupling between neighboring qubits and resonators. We incorporate a detailed understanding of the two-qubit Hamiltonian in order to extract the qubit control-line crosstalk, and utilise measurement-induced dephasing to directly characterize resonator control-line, as well as measurement crosstalk. |
Thursday, March 7, 2019 12:39PM - 12:51PM |
S35.00006: Superconducting Qubits Integrated with Superconducting Through-Substrate Vias (TSVs): Fabrication Donna-Ruth Yost, Mollie E. Schwartz, Danna Rosenberg, Justin Mallek, Rabindra Das, Alexandra L Day, David K Kim, Bethany M. Niedzielski, Alexander Melville, Wayne Woods, Jonilyn L Yoder, Andrew James Kerman, William D Oliver Three-dimensional integration (3DI) is a promising approach to provide increased connectivity for complex arrays of superconducting qubits while maintaining qubit performance. In this talk we describe our process flow for fabricating wafers of superconducting through-substrate vias (TSVs) which may be integrated directly into superconducting qubit chips and/or bump bond integrated with high-coherence qubits to carry signals to and from the qubit layer. |
Thursday, March 7, 2019 12:51PM - 1:03PM |
S35.00007: Superconducting qubits integrated with superconducting through-substrate vias: Measurement Mollie E. Schwartz, Donna-Ruth Yost, Danna Rosenberg, Justin Mallek, Rabindra Das, Alexandra L Day, David K Kim, Alexander Melville, Bethany M Niedzielski, Jonilyn L Yoder, Andrew James Kerman, William D Oliver Three-dimensional integration (3DI) is an enabling technology for superconducting qubits as circuits become larger, more complex, and more highly-connected. One promising approach to 3DI is the vertical routing of signals through superconducting through-substrate vias (TSVs), which may be integrated directly into a superconducting qubit chip or may carry signals to and from a high-coherence qubit layer via an interposer chip. We discuss recent results demonstrating superconducting qubit control, readout, and integration with high-aspect ratio superconducting TSVs. |
Thursday, March 7, 2019 1:03PM - 1:15PM |
S35.00008: Multilayer Microwave Integrated Quantum Circuits: Part 1 Chan U Lei, Lev Krayzman, Suhas Ganjam, Teresa L Brecht, Christopher J Axline, Yiwen Chu, Luke Burkhart, Luigi Frunzio, Robert J Schoelkopf Recently, superconducting quantum circuits have advanced from circuits containing few qubits to larger-scale ones with several tens of qubits. In order to increase the computational power of these circuits, many more circuit elements need to be integrated without degrading coherence of the individual components. Although the number of lithographic-precision elements in fully-planar (2D) circuits can be scaled up, it is very challenging to maintain interconnects and suppress decoherence induced by crosstalk as the circuits grow. On the other hand, three dimensional (3D) circuits which use conventionally-machined cavities to engineer the electromagnetic environment offer superior coherence but are challenging to scale up. In this talk, we discuss the multilayer microwave integrated quantum circuit (MMIQC), a platform which combines planar circuits with 3D superconducting enclosures to gain scalability while maintaining coherence. |
Thursday, March 7, 2019 1:15PM - 1:27PM |
S35.00009: Multilayer Microwave Integrated Quantum Circuits: Part 2 Lev Krayzman, Chan U Lei, Suhas Ganjam, Teresa L Brecht, Christopher J Axline, Yiwen Chu, Luigi Frunzio, Robert J Schoelkopf High-quality superconducting bonds are a critical element in constructing multilayer microwave integrated quantum circuits (MMIQCs). In order to provide lithographic precision for 3D enclosures made in wafers, it is necessary to create cavities with a high aspect ratio which places the seam in a region of high current density. In this talk, we describe a model for quantifying the loss associated with the seam, present our progress on indium bonding in microwave circuits, and discuss its application in scalable 3D superconducting quantum circuits. |
Thursday, March 7, 2019 1:27PM - 1:39PM |
S35.00010: Development of superconducting connection by flip-chip bonding for a multilayer superconducting quantum annealing machine Kazumasa Makise, Masaaki Maezawa, Mutsuo Hidaka, Hiroshi Nakagawa, Katsuya Kikuchi, Shiro Kawabata To realize practical-scale quantum annealing machines, a large number of qubits are required for the quantum processor. However, implementation of high-density qubits-array on a chip is a difficult problem because the size of qubits is limited by the size of wiring layer, Josephson junction and SQUID. To solve this problem, we have proposed an “QUIP” (Qubit-chip, Interposer and Package-substrate) a 2.5-dimensional (2.5 D) packaging structure. Therefore, development of the packaging technology of qubits is one of the most important issue for QUIP. In this presentation, we focus on flip-chip bonding (FCB) connection as a 2.5 D mounting method. We design and fabricate circular lead/indium alloy solder bumps with a 10 um diameter and 5 um height on the top chip and Nb/Ti/Au-opposing-contact pads on the base chip to form a daisy chain of over 10000 chip-to-chip interconnects. The electrical transport measurements are performed in a cryocooler using a standard dc four-probe technique. We observe a critical current for the daisy chain devices with 15000 bump array, Ic ~ 4 mA. |
Thursday, March 7, 2019 1:39PM - 1:51PM |
S35.00011: Intel Superconducting Qubits, Part 1: Performance improvements towards enabling quantum applications Roman Caudillo, David Michalak, Lester Lampert, Adel A Elsherbini, Javier A Falcon, Ye Seul Ashley Nam, Preston T Myers, Sonika Johri, Xiang Chris Zou, Jeanette Marie Roberts, Alessandro Bruno, Nandini Muthusubramanian, Cornelis Christiaan Bultink, Filip Malinowski, Nadia Haider, Leonardo DiCarlo, Jim Clarke Quantum processors based on superconducting materials with flux-tunable transmon qubits present many challenges, including minimizing flux and microwave crosstalk, improving qubit frequency targeting, extending coherence times, and ultimately maximizing gate fidelities. Here we present our fabrication capabilities addressing some of these challenges on die sizes ranging from small laterally wirebonded 2-qubit chips to larger flip-chip, ball-grid-array-bonded 7- and 17-qubit chips. Through improved die processing, including better-controlled materials interfaces, integration of air bridges, and Josephson Junction fabrication optimization, we demonstrate low flux and microwave crosstalk and qubit performance improvements resulting in one- and two-qubit gate fidelities that enable algorithm exploration and execution. |
Thursday, March 7, 2019 1:51PM - 2:03PM |
S35.00012: Intel Superconducting Qubits, Part 2: Integration on through-silicon-via (TSV) substrates. David Michalak, Roman Caudillo, Lester Lampert, Adel A Elsherbini, Javier A Falcon, Ye Seul Ashley Nam, Preston T Myers, Jeanette Marie Roberts, Alessandro Bruno, Nandini Muthusubramanian, Cornelis Christiaan Bultink, Filip Malinowski, Nadia Haider, Leonardo DiCarlo, Jim Clarke Quantum computing holds the potential for significantly improving computing speed relative to classical computing for selected algorithms and applications. Many researchers using transmons in a circuit QED quantum hardware architecture are producing chips with ever-increasing numbers of qubits. The corresponding increase in chip size shifts the cavity/drum resonant modes into a frequency range where qubits could be adversely affected. One solution is to implement through-silicon-vias (TSVs) and chip/cavity contact pins to supply more ground connections. We present recent microwave modeling and fabrication results on qubit chips containing membrane-covered TSVs. These flip chips are assembled using a ball-grid-array die-package interface for signal I/O. |
Thursday, March 7, 2019 2:03PM - 2:15PM |
S35.00013: 3D Integration of Superconducting Qubits in a Three-Tiered Quantum Processor Justin Mallek, Donna-Ruth Yost, Rabindra Das, Danna Rosenberg, Vladimir Bolkhovsky, Greg Calusine, Matthew Cook, Evan Golden, David K Kim, Alexander Melville, Bethany M Niedzielski, Mollie E. Schwartz, Corey Stull, Sergey Tolpygo, Wayne Woods, Jonilyn L Yoder, William D Oliver Heterogeneous 3D integration is an enabling technology for the construction of a quantum processor with a large number of superconducting qubits and a high degree of qubit interconnectivity. Our approach entails the construction of a three-tiered quantum processor where the high-coherence superconducting qubits are controlled and read-out through superconducting through silicon vias (TSVs) in an interposer which is bump bonded to a superconducting multichip module using indium microbumps. We will discuss our work on the fabrication and integration of the interposer with superconducting TSVs as well as the superconducting multichip module and the electrical data measured from test structures. |
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