Session C30: I/O, Packaging, and 3D Integration for Superconducting and Semiconductor Qubits I

Live

We have designed, fabricated, and measured an advanced quantum annealing processor comprised of 25 capacitively-shunted flux qubits (CSFQs) connected by 40 rf-SQUID tunable couplers. Each CSFQ features state-of-the-art persistent current readout (https://arxiv.org/abs/2006.10817). Over 200 dedicated bias lines enable unprecedented control over annealing schedules. To achieve the required scale and signal density while maintaining high coherence, we leverage MIT Lincoln Laboratory’s 3-tier stack fabrication and 3D integration process. We detail a novel design approach where the control and readout circuitry are routed through multiple chip tiers to create a modular architecture, and discuss how the device opens new horizons for both algorithm and hardware prototyping.   

Live

Flux tuning is an important ingredient in superconducting quantum circuits, particularly for the operation of fast, high-fidelity entangling gates. Conventional circuit QED implementations use on-chip flux bias lines (FBLs) to achieve fast local biasing of circuit elements, such as transmon qubits and tunable couplers. These FBLs can suffer from high levels of non-local crosstalk due to uncontrolled current flow in the ground plane of the device, as well as substrate heating. Here we demonstrate a 3D-integrated architecture for off-chip local flux tuning of gradiometric coaxial transmon qubits, with low crosstalk and large bandwidth. The high selectivity of our FBL design is achieved by optimally matching its geometry and orientation to the circuit on the chip. We characterize flux crosstalk, bandwidth and noise properties of this system, and show that it is compatible with the operation of fast entangling interactions, such as parametrically activated gates. Additionally, this FBL implementation considerably reduces device complexity by removing the need for bonding, ground planes and air bridges on the substrate.   

Live

The superconducting qubit platform has advanced over the past twenty years from fundamental exploration to the deployment of many-qubit systems that support complex algorithms. Along the way, 3D integration has emerged as a critical enabling technology for control and measurement of qubits in an extended array. While 3D integration has long been used in classical computing hardware, the normal metals and lossy dielectrics in these systems are incompatible with high-coherence quantum circuits. 3D integration techniques must therefore be developed and vetted specifically in the context of coherent quantum devices.

Here, we describe a three-tier approach to 3D integration for superconducting qubits, comprising: a planarized, superconducting multilayer metallization chip; an interposer featuring compact, high-aspect ratio, superconducting thru-silicon vias (TSVs); and a qubit chip. These chips are connected to each other via low-loss indium bump bonds. Together, they form a “three-stack” that merges the routing capabilities of the multilayer chip with high-coherence qubits; the interposer provides signal transfer while isolating qubits from lossy dielectrics on the routing chip, and enables new, compact, TSV-integrated circuit element design. I will review the three-stack and its uses, describe experiments that validate the three-stack architecture, and introduce novel circuits and designs that leverage the unique capabilities of the three-stack.   

Live

We demonstrate state-of-the-art qubit coherence and single-qubit gate fidelities in a readily extensible superconducting circuit architecture. Our 4-qubit device features 3D integrated off-chip control wiring, readout-resonators fabricated on the reverse-side of the circuit substrate, and an inductively shunted enclosure. We establish these technologies are compatible with high qubit coherence, measuring average T₁ = 148 µs. We provide a careful experimental analysis of packaging crosstalk and show that the off-chip wiring is highly selective. The coherence and crosstalk results are borne out in simultaneous randomized benchmarking, where we measure average single-qubit gate fidelities >99.98%. By considering band-structure, we show the device contains a unit-cell that can tile the plane while still providing a clean electromagnetic environment for qubits; with spatially exponentially decaying packaging crosstalk between qubits. Our results demonstrate a promising 3D integrated architecture for creating large 2D arrays of superconducting qubits, using current superconducting qubit fabrication techniques.   

Live

We describe a 3D-integrated 3-tier stack architecture for superconducting quantum circuits to enable enhanced connectivity while preserving qubit coherence. The top tier is fabricated using dielectric-free (single-layer) processing that supports high qubit coherence; the bottom tier has multiple superconducting metal layers coupled via interconnects through oxide layers for advanced DC and RF signal routing;; and an intermediate interposer tier is bump-bonded to the other two to provide spatial separation between them while achieving electrical connectivity through the full stack using superconducting through-silicon vias (TSVs) and indium bumps. Robust, high-yield connectivity between the three tiers is confirmed using metal chains with thousands of links that traverse the three tiers.   

Live

As quantum systems reach the scale needed for a broad range of quantum computing applications, engineers are addressing the challenge of developing robust systems-level readout and control of multi-qubit systems. The interposer in the 3-stack integration approach provides access to multi-level superconducting circuitry through superconducting through-silicon vias (TSVs) while preserving qubit performance by isolating the qubits from lossy dielectrics in the routing tier. Our active interposer also provides additional levels for resonators and qubits to be integrated into the system and enables novel circuit elements that incorporate TSVs. We present our fabrication process for this active interposer tier, as well as characterization data for superconducting TSVs and qubits.   

Live

We demonstrate the operation and local control of high-coherence capacitively-shunted flux qubits (CSFQs) in a 3D-integrated 3-tier architecture. Qubits are fabricated both on the qubit and interposer tiers using high-coherence processes. Readout and control components, including resonators and flux bias lines, are located on the interposer tier, and are accessed through superconducting through-silicon vias (TSVs) and bump bonds from a bottom-tier multi-layer superconducting multichip module (SMCM). Coherence of the CSFQs in the 3D-integrated stack is consistent with values typical for the single-tier processes – including with the dielectric-containing multilayer SMCM tier electrically coupled through the three-tier stack.   

Live

Adoption of fast, parametric coupling elements has improved the performance of superconducting qubits, enabling recent demonstrations of a quantum advantage in randomized sampling problems. The development of low loss, high contrast couplers is critical for scaling up these systems. We present a blueprint for a gate-tunable coupler realized with a two-dimensional electron gas in an InAs/InGaAs heterostructure. Our numerical simulations yield an on/off ratio of over two orders of magnitude. We give an estimate of the dielectric-limited loss from the inclusion of the coupler in a two qubit system.   

Live

While recent progress on superconducting quantum circuits has enabled us to realize intermediate-scale quantum processers, we need to scale up the number of qubits even more to realize a fully fault-tolerant quantum computer. One of the biggest challenges when scaling up the two-dimensional array of qubits is to wire control and readout lines to every qubit in use. The wiring from the side of a chip becomes more difficult with an increased number of qubits. To overcome this difficulty, we propose scalable packaging and wiring schemes based on the vertical connection of coaxial cables from the bottom of the chip. The vertically connected cable and qubit structure enables us to treat the unit structure as a module and scale it up by tiling the same structure in two dimensions. We will present the design and performance of our chip and package. We also discuss the scalability of this scheme by focusing on the spurious mode and cross-talk.   

Live

Solid-state qubits with transition frequencies in the microwave regime, such as superconducting qubits, are at the forefront towards the realization of practical quantum processors. However, the high-fidelity and simultaneous control over these qubits remains a challenge in achieving quantum computation at scale. Multiple, often interrelated factors such as spurious modes, conduction losses, and crosstalk impose challenges that require a comprehensive approach to package design. Here, we provide an overview of our recent work aimed at systematically addressing these challenges, including mode suppression, chip-to-board interconnect design, interposer design, and material choices. We present results from simulations and demonstrate the corresponding physical characterization of the electromagnetic environment of the qubit.   

Live

We have designed, fabricated, and measured an advanced quantum annealing processor comprised of 25 capacitively-shunted flux qubits (CSFQs) connected by 40 rf-SQUID tunable couplers. Each CSFQ features state-of-the-art persistent current readout (https://arxiv.org/abs/2006.10817). Over 200 dedicated bias lines enable unprecedented control over annealing schedules. To achieve the required scale and signal density while maintaining high coherence, we leverage MIT Lincoln Laboratory’s 3-tier stack fabrication and 3D integration process. We show data validating key aspects of the novel modular architecture where control and readout circuitry traverse multiple tiers. We discuss initial qubit measurements, and the versatility of the architecture for algorithm and hardware prototyping.   

Live

We discuss a new architecture for superconducting qubits which uses multilevel wiring built off of advanced packaging techniques such as indium bump bonds and through-silicon vias. This architecture improves the scalability of quantum processor design by simplifying I/O routing and reducing crosstalk without sacrificing qubit coherence. Measurement results of a 6-qubit demonstrator chip will be reported, including qubit coherence, pair-wise qubit gate performance and characterization of the individual packaging elements used in the structure.   

Live

Scaling challenges that arise from increasing the qubit count and interconnect density in quantum circuits requires the development of novel microwave and cryogenic packaging solutions. Beyond approximately 50 qubits, a perimeter chip interface becomes the limiting factor for scalability and 3D signalling solutions are required to control a large number of qubits. We present a 3D package that leverages existing vertical interconnect technology and newly developed chip interface management for cryogenic environments. This approach allows us to individually control and measure the qubits on a larger scale without compromising signal integrity.