Session X17: Fabrication of Silicon Qubits

State-of-the-art Quantum Dot devices from a full 300mm process line: towards scalable spin qubit devices

Intel continues with its efforts towards the fabrication of spin qubit devices in a full 300mm process line. Significant progress has been achieved on the fin-based process flow that yields QD devices with performance comparable to academic’s state-of-the-art devices. Among other important milestones of this work is the implementation of fin-to-fin charge sensing which is needed to operate in the single electron regime. We will also present updates on wide linear array devices as well as the current status of spin qubit device fabrication; both are key to the long-term implementation of scalable spin qubit devices in silicon for quantum computing technology.   

The impact of using palladium gates for silicon quantum dot fabrication: defect densities and strain

Quantum dots (QD) in the silicon MOS system benefit from the use of palladium or platinum for gate materials because the small grain size of these metals compared to aluminum aids in shrinking the gate and dot dimensions. However, it is not clear what differences arise with respect to process-induced defect density and homogeneous strain. Here, we present measurements of oxide defect densities (fixed charge and interface trap density) as a function of forming gas anneal temperature for three different gate metals: Al, Ti/Pd, and Ti/Pt. We also investigate the concomitant effect of these anneals on the mechanical properties of the gate material, such as the intrinsic film stress, coefficient of thermal expansion, and bi-axial modulus. Our initial results indicate that Ti/Pd and Ti/Pt result in much higher fixed charge density and higher, though comparable, interface trap densities when compared to Al. These results provide guidance on adjusting QD fabrication for these gate materials.
  

Revising the point-charge model for dopants in Si and applications to atomic-scale system simulations

Dopants in silicon are strong candidates for qubits in scalable solid-state quantum systems. Tight-binding (TB) theory has been used to provide a good atomic-scale model with reasonable precision when a central cell correction is adjusted to fit to experimental binding energies for one choice of the bulk Si TB parameters. However, this simple model fails to predict the correct dopant level energy degeneracies for many other well-established bulk Si TB models. We argue that the point-charge dopant model with a simple central cell correction is missing vital contributions from the dopant potential that must be included to encapsulate the underlying physics. We have developed a dopant model that includes several new corrections that are obtained explicitly using atomic orbitals to evaluate the appropriate dopant matrix elements rather than by fitting to experiment. We find that these new corrections play a critical role in defining the dopant physics, as all bulk Si TB parameters predict the correct ordering of dopant levels in our new model. Results are discussed to show the effect on interdopant exchange coupling and the level structure of dopant clusters. Finally, we discuss how these models can be utilized to effectively simulate many-body physics in atom chains and arrays.   

Low-frequency electron spin-qubit detuning noise in highly purified 28Si/SiGe

The manipulation fidelity of a single-electron spin qubit gate-confined in a ²⁸Si/SiGe quantum dot has recently been drastically improved by nuclear isotope purification [1]. Here, we characterize a ²⁸Si/SiGe device with an embedded nanomagnet, a large valley splitting (> 0.2 meV [2]), and a remaining ²⁹Si concentration of only 60 ppm in the strained silicon quantum well layer, which is grown by molecular beam epitaxy. We identify the combination of charge noise and gradient magnetic field as the dominant source of low frequency qubit detuning noise. The power spectral density (PSD) of the charge noise explains the frequency-dependence of the detuning noise PSD, as well as the observation of a decreasing time-ensemble spin dephasing time with increasing measurement time over several hours [3]. We also comment on the role of the remaining nuclear spins in the SiGe barrier on the qubit dephasing and the origin of the observed large valley splitting.
[1] J. Yoneda, et al., Nat. Nanotechnol. 13, 102 (2018).
[2] A. Hollmann et al., arXiv:1907.04146.
[3] T. Struck et al., arXiv:1909.11396.   

Single-electron control in a foundry-fabricated 2D array of silicon quantum dots

Two-dimensional quantum dot arrays constitute a useful platform for spin-qubit processors and condensed matter simulations. With the advent of foundry-fabricated silicon qubits [1], larger CMOS quantum dot arrays become increasingly promising for implementing multi-qubit devices. We use a 2x2 array of quantum dots, fabricated fully at CEA-LETI using industrial silicon-on-insulator technology, to reconfigure the array as single, double, triple, or quadruple dots, and use dispersive charge sensing to deplete all dots down to the last electron. Combining high-frequency reflectometry with pulsed-gate techniques, we tune tunneling rates and demonstrate the shuttling of individual electrons within the two-dimensional array.

[1] Maurand, R. et al. A CMOS silicon spin qubit. NatureCommunications 7, 13575 (2016).   

Spin Qubits Confined to a Silicon Nano-Ridge

Electrostatically defined quantum dots (QDs) in silicon are an attractive platform for quantum computation based on electron spin qubits. Si qubit devices have been demonstrated by the modification of industrial FinFETs [1]. We propose a scalable qubit device fabricated by industry-compatible processes such as damascene and spacer processes [2].
The device consists of a double array of QDs formed along a silicon nano-ridge. We implement TiN side-gates, a global back-gate and a dense metallic top-gate array for controlling the QDs potentials. In order to minimize potential fluctuations caused by interface roughness and charged defects at the Si/SiO₂ interface, the nano-ridge is anisotropically etched and exhibits atomically flat {111} facets. We characterized its interface roughness and the defect density of the Si/SiO₂ interface. The most relevant process modules are experimentally demonstrated including local oxidation of the silicon nano-ridge, side-gate formation and top-gate fabrication using a low-pitch self-aligned spacer process.

[1] B. Voisin et al., Nano Lett. 14, 2094 (2014).
[2] J. Klos et al., Appl. Sci. 9, 3823 (2019).   

Silicon spin qubit development in a 300 mm integrated process

Semiconductor spin qubits are developing at a rapid pace with increasing qubit coherence times and quantum gate-fidelities over the last years [1]. This progress has resulted in multiple proposals for large-scale spin qubit-arrays [2-4]. However, scaling up existing qubit prototypes to several qubit arrays require advanced fabrication techniques.
We address this challenge by employing a state-of-the-art 300mm fabrication process [5-6]. In this talk, we present the integration of Si-MOS spin qubit devices in an hybrid integration scheme, which combines e-beam and optical lithography. This enables fast turn-around times while still offering the necessary qubit design flexibility. Furthermore, industrial-scale characterization allows for the room temperature statistical extraction of key device and material parameters. This data and its correlation to low temperature device performance will be discussed, along with the main challenges for further development.

[1] Yoneda et al., Nature Nanotech. 13 (2018)
[2] Li et al., Science Adv., 4(7) (2018)
[3] Veldhorst et al., Nature Comm., 8(1) (2017)
[4] Mohiyaddin et al., Proc. of IITC (2019)
[5] Govoreanu et al., Silicon Nanoelectronics Workshop (2019)
[6] Kubicek et al., SSDM (2019)   

Industrial quantum dot arrays for spin-qubit quantum computation by all-optical 300mm lithography

Using quantum dot arrays fabricated in a 300mm process line, we demonstrate well-controlled single and double quantum dots formed in an isotopically enriched ²⁸Si-MOS substrate. These devices are fully fabricated with optical lithography, plasma etching, and chemical-mechanical polishing techniques for patterning, compatible with state of the art industrial fabrication.
In the many-electron regime independent tunnel-barrier control is shown, a prerequisite for high-fidelity two-qubit control. Data driven process improvements of the quantum dots have led to a significant increase in charge-sensing sensitivity capable of single shot read-out
Using state of the art charge detection methods, we are able to observe single-electron occupation of these quantum dot arrays. The few-electron regime shows stable device behavior, with dots forming both under the plunger and barrier gates. The occurrence of spurious dots is analyzed.
Here, we will show our latest results on utilizing these quantum dot arrays as spin-qubits.   

Pauli spin blockade for holes in a hot silicon FinFET

Quantum information can be encoded in the spin state of a single electron or hole confined to a semiconductor quantum dot (QD) (Loss and DiVincenzo, PRA57, 120 (1998)). Silicon is a particularly promising platform for scalable spin-based quantum computing due to its fully developed, industrial manufacturing processes. Furthermore, a nearly nuclear-spin-free environment can be engineered by means of isotopic purification. Holes in silicon are of particular interest, since they are subject to a strong spin-orbit-interaction, allowing for fast, all-electrical spin manipulation (Maurand et al., Nature Comm. 7, 13575 (2016)).
We define single and double QDs in a FinFET-like device architecture. A second gate layer, which is fabricated in a self-aligned process, allows for in-situ adjustments of the tunnel couplings and makes these devices highly tunable. In addition, conventional impurity-doped source and drain contacts are replaced in an overlapping-gate structure by a metallic silicide. We observe Coulomb blockade and, furthermore, Pauli spin blockade for both electrons and holes. The large singlet-triplet splitting allows spin blockade for holes to be observed at temperatures as high as 10 K, paving the way for a hot spin-qubit.   

Crossbar architecture with individually addressable single electron transistors

Achieving sublinear scaling of interconnects between room temperature equipment and cryogenic hardware is essential in engineering a practical spin based quantum computer. This requirement is equally present in high throughput characterization for the device fabrication-measurement cycle. In addition to cryogenic multiplexing, the lines into the cryostat can be further reduced at the qubit plane. Here, a sparse crossbar architecture of single electron transistors (SETs) is presented, allowing for the formation of a quadratic number of unique SETs with linearly increasing control lines. We show experimental effort toward realizing crossbars which are operated using a CMOS multiplexer consisting of commercial components at 50 mK capable of supporting up to 648 SETs. These structures provide insight into shared control, enable statistical characterization of substrate uniformity and serve as a platform for device design optimization. Furthermore, by evolving the unit cell, such structures can act as stepping-stones towards proposed fully-coupled crossbar qubit architectures and integration of cryogenic electronics.   

Silicon quantum dot fabrication with subtractive processing

The overlapping aluminum gate design for silicon quantum dot qubits has shown success in the formation of one and two qubit systems. However, charge noise and device consistency are still major points of concern for silicon quantum systems. Here, we present an alternative approach to silicon quantum dot fabrication, utilizing negative-tone e-beam lithography and subtractive processing to replicate the typical three-layer aluminum gate structure with two layers of palladium gates. Using high-precision HSQ e-beam resist, all plunger, barrier/tunnel, and accumulation gates can be fabricated as a single layer. This eliminates overlay issues and ensures barrier gates, typically written as the third layer, have large action on the dots. The self-oxidation of the three aluminum gate layers is replaced with a single layer of deposited dielectric. Progress towards the realization of a well-controlled, lower noise quantum dot system using etched palladium gates will be presented.   

Charge and Hybrid Qubits in 22nm FDSOI process

A number of recent studies report the achievements of silicon-based qubits. Furthermore, the benefits of nanometer-scale CMOS technologies boost the potential of miniaturization, scalability and full system integration for quantum computers. This abstract presents the recent development of a quantum system-on-a-chip utilizing quantum structures fabricated in 22nm FDSOI. The main challenge of achieving deep cryogenic operation for the mixed-signal classic circuit controlling the quantum core was surpassed by using programmable local heating DACs that slightly boost the local temperature of the die, which needs to be maintained around 4 K. A staged multi-phase operation was adopted for the digital core in order to minimize the quantum decoherence originated in digital noise injection.

We show that the fabricated quantum structures can be used to realize charge and/or hybrid qubits. The theoretical analysis and modeling of qubits are based on a Hubbard model in the tight-binding limit. Different types of qubits (for instance, spin, charge or hybrid) have been examined. Various topologies of interacting qubits are investigated exhibiting maximally entangled states. Preliminary experimental results are also presented.   

Improving Gate Dielectrics for Reducing Charge Noise in Si/SiGe Quantum Dots

We report on the materials development of a novel low temperature SiO₂ gate dielectric for use in Si/SiGe quantum dot devices. X-ray Photoemission Spectroscopy (XPS) measurements show nitric acid oxidation of silicon (NAOS) or silicon-germanium alloys produces a more stoichiometric and thicker silicon oxide over other low temperature techniques [1]. Using this approach, we create a ~1.7 nm SiO₂ gate dielectric over the active region of a Si/SiGe quantum dot device coupled to a Nb microwave resonator for charge state readout. By measuring the current noise in a quantum dot we observe a 1/f power spectral density of chemical potential noise with an amplitude of 0.203 μeV²/Hz at 1 Hz which compares favorably to similar devices using ALD Al₂O₃ and native SiO₂ [2]. Further, we demonstrate low frequency Landau-Zener spectroscopy of a double dot charge qubit and discuss cavity-charge coupling experiments [3,4].

References:
[1] H. Kobayashi et al. Applied Surface Science 256 (19) 5744 (2010).
[2] E. J. Connors et al. Preprint at https://arxiv.org/abs/1907.07549
[3] S. N. Shevchenko et al. PRB 98, 195434 (2018)
[4] X. Mi et al. Phys. Rev. B 98, 161404 (2018)
  

Charge noise in Si/SiGe quantum dots

Electron spins in silicon have long coherence times and are a promising qubit platform. However, electric field noise in semiconductors poses a challenge for most single- and multi-qubit operations in quantum-dot spin qubits. Here, we investigate the dependence of low-frequency charge noise spectra on temperature and aluminum-oxide gate dielectric thickness in Si/SiGe quantum dots with overlapping gates. We find that charge noise increases with aluminum oxide thickness. Additionally, we observe strong dot-to-dot variations in the temperature dependence of the noise magnitude and spectrum. These findings suggest that each quantum dot experiences noise caused by a distinct ensemble of two-level systems, each of which has a non-uniform distribution of thermal activation energies. Taken together, our results suggest that charge noise in Si/SiGe quantum dots originates at least in part from a non-uniform distribution of two-level systems near the surface of the semiconductor.