Silicon spin qubit development in a 300 mm integrated process*

Semiconductor spin qubits are developing at a rapid pace with increasing qubit coherence times and quantum gate-fidelities over the last years [1]. This progress has resulted in multiple proposals for large-scale spin qubit-arrays [2-4]. However, scaling up existing qubit prototypes to several qubit arrays require advanced fabrication techniques.
We address this challenge by employing a state-of-the-art 300mm fabrication process [5-6]. In this talk, we present the integration of Si-MOS spin qubit devices in an hybrid integration scheme, which combines e-beam and optical lithography. This enables fast turn-around times while still offering the necessary qubit design flexibility. Furthermore, industrial-scale characterization allows for the room temperature statistical extraction of key device and material parameters. This data and its correlation to low temperature device performance will be discussed, along with the main challenges for further development.

[1] Yoneda et al., Nature Nanotech. 13 (2018)
[2] Li et al., Science Adv., 4(7) (2018)
[3] Veldhorst et al., Nature Comm., 8(1) (2017)
[4] Mohiyaddin et al., Proc. of IITC (2019)
[5] Govoreanu et al., Silicon Nanoelectronics Workshop (2019)
[6] Kubicek et al., SSDM (2019)