Pipeline architecture for a silicon qubit processor*

Noisy intermediate-scale quantum (NISQ) devices seek quantum speedup over classical systems without full quantum error correction. We propose a NISQ processor architecture using a qubit pipeline in which all run-time control is applied globally, simplifying the number and complexity of required control and interconnect resources. This is achieved by progressing qubit states through a layered physical array of structures which realise single- and two-qubit gates. Such approach lends itself to NISQ applications such as variational quantum eigensolvers requiring repetitions of the same calculations, or small variations thereof. In exchange for simplified run-time control, a larger number of physical structures is required for shuttling the qubits as the circuit depth now corresponds to a physical axis of grid structures. However, qubit states can be pipelined through the arrays densely for repeated runs to make more efficient use of physical resources. This architecture is well suited to silicon quantum dot electron spin qubits due to their high density and scalability. We demonstrate how the key elements of single- and two-qubit gates and qubit state shuttling can be implemented in the silicon spin-qubit platform for the qubit pipeline.