Bulletin of the American Physical Society
APS March Meeting 2020
Volume 65, Number 1
Monday–Friday, March 2–6, 2020; Denver, Colorado
Session L57: 2D Electron Devices and TransportFocus
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Sponsoring Units: APS Room: Mile High Ballroom 3A |
Wednesday, March 4, 2020 8:00AM - 8:12AM |
L57.00001: Complementary logic inverters based on polarity-controllable MoS2 fin-shaped and v-shaped field effect transistors Che-Yu Lin, Po-Chun Chen, Ming-Cheng Chen, Ming-Yang Li, Lain-Jong Li, Kai-Shin Li, YannWen Lan Integration of high performance n-type and p-type field-effect transistors with complementary device operation in the same kind of layered materials is highly desirable for pursuing low power and flexible next-generation electronics. In this work, we show a well-mannered growth of MoS2 between two electrodes on silicon oxide with fin-shaped and v-shaped structure. In the fin-shaped case, both n-type and p-type MoS2 can be integrated by using a traditional implantation technique. In the v-shaped case, the device can alternately operate either as a p-type or an n-type semiconductor in the identical one. The proposed device is built with an adjustable threshold voltage (Vth), which can be varied by adding a layer of plasma-oxidized dielectric at the top gate structure. Consequently, the Vth shifts and the top gate structure switch from the typical n-type to p-type while n-type behaviour remains in the application of bottom-gate voltages. In both cases, we have accordingly demonstrated the complementary logic inverters based on the polarity-controllable behavior. Our results provide evidence for complementary 2D materials operation in the same materials, a promising avenue for the development of high-density complementary 2D electronic devices. |
Wednesday, March 4, 2020 8:12AM - 8:24AM |
L57.00002: Device simulation study of ion-gated ambipolar transition-metal dichalcogenide transistors Akiko Ueda, Yijin Zhang, Hiroshi Imamura, Yoshihiro Iwasa Ion gating is known as a powerful tool to access electronic functionalities with low voltage operation. Though many interesting experimental studies have been reported, the device simulation had never been performed before. In this work, we developed a two-dimensional layer transistor model based on the drift-diffusion method for an ionic liquid (IL) as a gate dielectric. We reproduced the transport characteristics of the ion-gated WSe2 transistors reported in several experiments and explained the transport mechanism using the band profile and spatial distribution obtained by the calculation. In particular, the simulation explains the ambipolar behavior with the gate voltage comparable to the band gap energy, as well as the formation of p-n junctions in the channel reported in several experimental papers. The simulation clearly shows that the ambipolar behavior becomes possible by the dramatic change of the potential profile at the contacts. The developed model is highly advantageous for exploring the functionalities and design ideal devices for ion-gated transition-metal dichalcogenide transistors. |
Wednesday, March 4, 2020 8:24AM - 8:36AM |
L57.00003: Hybrid Transfer of 2D materials: An approach towards a wrinkle and contaminations free transfer of 2D materials grown on metallic substrates for van der Waals heterostructures and large scale industrial applications. Sajith Withanage, Tharanga Nanayakkara, U. Kushan Wijewardena, Annika Kriisa, Ramesh Mani There has been much recent interest in transferring 2D materials on to non-conducting surfaces. One approach was to pick-up graphene grown by the CVD method using a flake of hexagonal boron nitride (hBN) to have a contamination-free dry transfer. [1] But this kind of transfer technique can be only used in small-scale device fabrication for laboratory use since the scale limitations of the hBN flakes and the limited supply of hBN flakes with low thicknesses. Here, we report a hybrid transfer technique that combines wet and dry transfer processes using polymer support resulting in wrinkle and contamination-free high mobility 2D materials. Thus, we detail the transfer process, conditions for a successful transfer and the quality of CVD grown graphene. The transferred graphene layers are characterized by various methods, and the results of the study are reported. |
Wednesday, March 4, 2020 8:36AM - 8:48AM |
L57.00004: Magnetotransport studies in hybrid 2D/0D nanostructures Ethel Perez-Hoyos, Yunqiu (Kelly) Luo, Abhilasha Dehankar, Jinsong Xu, Daniel Pharis, Roland Kawakami, Jessica Winter, Ezekiel Johnston-Halperin We introduce a device fabrication strategy that takes advantage of stacking techniques developed for van der Waals heterostructures to construct hybrid 2D/0D composite magnetic nanostructures, with potential application in the study of spin and charge disorder as well as magnetic-proximity effects. The structures in this study are comprised of superparamagnetic iron oxide nanoparticles (SPIONs) and monolayer graphene. The SPIONs are deposited first using a Langmuir-Blodgett technique, yielding rafts of highly ordered nanoparticles (Fig.1b). Characterization via magnetic force microscopy (MFM) reveals magnetic order at multiple length scales and SQUID magnetometry identifies both glassy antiferromagnetic and ferromagnetic response. Single graphene monolayers are mechanically stacked on the SPIONs layer, and characterized via low temperature magneto-transport. Initial measurements show good electron mobility in the graphene layer and indications of exchange coupling between the graphene and the SPIONs layer. Measurements in the quantum Hall regime will be discussed. |
Wednesday, March 4, 2020 8:48AM - 9:00AM |
L57.00005: Electron Transport of Germanium Sulfide Field- Effect Transistor Using Layered Black Phosphorus Abrar Alhazmi, Malak Albogami, Olaiyan Alolaiyan, Mohammed R Amer Layered 2D materials have recently attracted attention due to their unique electrical and optical properties. In particular, Germanium Sulfide(GeS) which has been predicted to exhibit high mobility. However, few research work reported in the literature on GeS devices and they exhibit high contact resistance. The origin of this contact resistance is still not clear. Here, we investigate the electron transport of pristine GeS field effect transistors. A high contact resistance was observed. Various methods were used to overcome this issue including thermal, electrical annealing, and 2D heterojunction contact. Both annealing methods did not yield any improvement in the measured IVds. However, we observe an anomalous negative differential resistance(NDR) with low contact resistance and n-type conductivity when black phosphorus(BP) are deposited between GeS and S/D electrodes. This NDR is uncontrollable in ambient and insensitive to gate voltage. We believe this NDR is caused by chemical reaction between GeS and degraded BP where the measured electrical conductivity leads to chemical doping, causing the observation of conductivity switch from p-type for pristine GeS, to n-type for GeS with degraded BP contacts. Further investigations are needed to characterize the origin of this NDR. |
Wednesday, March 4, 2020 9:00AM - 9:12AM |
L57.00006: Contact Doped Multi-layer Tungsten Diselenide Field Effect Transistors Inyong Moon, Sungwon Lee, Minsup Choi, Won Jong Yoo According to the conventional transistor process including the silicon semiconductor device, it is the common practice to heavily dope contact regions under the metallic electrodes by using the ion implantation technique so as to minimize contact resistance. In this study, we demonstrate a contact doping technique applied to the ultra-thin (2~5 nm) tungsten diselenide (WSe2) channel formed in field effect transistors (FET) by applying the selective oxidation process to the contact regions. Using our devices that underwent the contact doping, we were able to achieve high performance p-type FET electrical properties with an on/off ratio of 108, a field effect mobility of 180 cm2/Vs and a contact resistance of 1 kΩμm. Importantly, Schottky barrier heights (SBH) and Fermi level pinning factors of the contact doped WSe2 FET were measured by employing various work function metals (In, Ti, Au, Pd) as the electrodes. We were able to derive the relationship between the Schottky barrier heights and the contact resistances very reliably. |
Wednesday, March 4, 2020 9:12AM - 9:48AM |
L57.00007: 2D NC-FET, FE-FET and FeS-FET Invited Speaker: Peide (Peter) Ye The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric dielectric as a negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. In this talk, we will review the recent progress on negative capacitance field-effect transistors (NC-FET) and ferroelectric field-effect transistors (Fe-FET) using TMDs as the transistor channels. [1,2] More importantly, a new device concept, which we call as ferroelectric semiconductor field-effect transistor (FeS-FET), was proposed and experimentally demonstrated. [3] In this novel FeS-FET, a 2D ferroelectric semiconductor α-In2Se3 is used to replace conventional semiconductor as channel. α-In2Se3 is identified due to its proper bandgap, room temperature ferroelectricity, the ability to maintain ferroelectricity down to a few atomic layers and the feasibility for large-area growth. |
Wednesday, March 4, 2020 9:48AM - 10:24AM |
L57.00008: Controlling optoelectronic properties of 2D semiconductors: band engineering and
moiré superlattices. Invited Speaker: Roman Gorbachev Van der Waals heterostructures is a unique class of layered artificial solids that offers |
Wednesday, March 4, 2020 10:24AM - 10:36AM |
L57.00009: New Approaches and Observations in Scaled Contacts for 2D FETs Zhihui Cheng, Hattan Abuzaid, Yifei Yu, Shreya Singh, Linyou Cao, Curt Richter, Aaron Franklin Atomically thin 2D crystals are promising channel materials for extremely scaled field-effect transistors (FETs). For devices at the scaled regime, both channel and contact length must be scaled, with channel length being the distance from source to drain contacts and contact length being the length of the source/drain covering the 2D semiconductor channel. Contacting 2D materials at these scaled contact lengths (< 30 nm) has rarely been pursued or studied in depth. Moreover, the device community has not yet determined how contacts can be scaled down without causing significant degradation in device performance; i.e., how long is the transfer length, below which current crowding effects appear? Here, we demonstrate new measurement approaches and results for determining the transfer length of MoS2 FETs by physically scaling the contact length. We found that, contrary to previous reports, top contacts can be scaled to ~20 nm without obvious degradation in transistor performance. Our data from measurements of over 100 devices with different contact lengths statistically imply that contact resistance variation increases in the scaled contact regime. Our work illustrates the impact of current crowding in scaled contacts and the ultimate scalability of metal-2D contact interfaces. |
Wednesday, March 4, 2020 10:36AM - 10:48AM |
L57.00010: Ultrasensitive molecular interaction in MoS2-graphene hybrid structure via electrostatic control Rahul Tripathi, Abha Misra Following the discovery of graphene, other 2D materials such as TMDs offer great potential for future sensing devices because of the high surface-to-bulk ratio. Moreover, electronic transport in vertically stacked atomically thin heterojunctions of 2D materials are extremely sensitive to the surrounding atmosphere, thus allowing their exploration in molecular sensing applications. We report the fabrication of designed vdW interfaces of few-layer graphene and MoS2 in vertical heterojunction and evaluation of electrical and molecular interaction. The few-layer MoS2-graphene with vertically stacked hybrid shows a non-linearity in the drain current due to barrier formation at the interface that can be modulated by an external electric field. The hetero p-n junction between MoS2 on graphene reveals superior molecular interaction with a high sensitivity of 18% at 10 ppb level of nitrogen dioxide in transfer characteristics near accumulation region at room temperature. We further observed that the recovery time of the device can be tuned using the switching behavior of the device depicting an overall superior sensing capability leading to an excellent advancement in sensing devices. Our findings offer significant insight into the MoS2-graphene heterostructure for molecular interaction. |
Wednesday, March 4, 2020 10:48AM - 11:00AM |
L57.00011: Monolayer-Bulk Black Phosphorus Natural Heterojunction Tunnel Field-Effect Transistor for Low Power Switches Seungho Kim, Sungjae Cho, Gyuho Myeong, Wongil Shin, Hongsik Lim, Boram Kim, Taehyeok Jin, Sungjin Chang, Kenji Watanabe, Takashi Taniguchi Transistor down-scaling by Moore’s law over fifty years enabled today’s information technology, but fundamental limits have ended Moore’s law [1]; Transistors require at least 60 mV switching voltage for each 10-fold current increase (subthreshold swing (SS) 60 mV/dec). Alternative tunnel field-effect transistors (TFETs) are widely studied to achieve a sub-thermionic SS and high I60 (current where SS becomes 60 mV/dec) [2]. Heterojunction (HJ) TFETs bear promise to deliver high I60, but experimental results do not meet theoretical expectations due to interface problems in the HJs constructed from different materials. Here, we report a natural HJ-TFET with spatially varying layer thickness in black phosphorus (BP) without interface problems. We achieved record-low average SS over 4–5 decades of current, SSave_4dec ≈ 22.9 mV/dec and SSave_5dec ≈ 26.0 mV/dec with record-high I60 (= 0.65–1 μA/μm), paving the way for the application in low power switches. |
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