3D Integration for Superconducting Qubits; Part 2 Superconducting Through Silicon Via Interposer Fabrication*

Quantum annealing requires addressing and connecting an array of qubits. Integration requirements are driven by performance requirements, including high connectivity, low dissipation, and high qubit coherence. In this talk we describe our process flow for fabricating wafers with superconducting through silicon vias (TSVs) leveraging commercial 3D integration tools and techniques. This work demonstrates a means to control and readout an array of superconducting qubits.