Session T20: Invited Session: Advanced Characterization of Transistor Gate Stacks and Interfaces

Directions in High-k Gate Stacks: From Silicon Chips to Carbon Nanomaterials

The successful implementation of high-k/metal gates for silicon CMOS has culminated a decade of research on metal-oxide interactions with silicon. The ability to profile materials on a nanometer length scale has greatly assisted our ability to tailor electrical properties to create functional devices. Initial concerns addressed with composition profiling (e.g. Si content, Hf diffusion, thermal stability) have been replaced by more advanced questions. For example, gate-first technologies often use threshold-modifying layers, whose electrical properties are closely linked with their depth distribution. Oxygen diffusion is another complex problem of current concern, where physical characterization by isotopic tracing has given valuable insights. A similar set of challenges will confront us in creating carbon-based devices. Much effort is focused on nucleation of dielectrics, along with stability and interactions with the channel. This parallels work in the early development of high-k/Si. This talk will review some important lessons from the past decade, and discuss how we can apply this knowledge to creating improved graphene-channel devices.   

Nanometer-scale properties of metal/oxide interfaces and ``end-on'' metal contacts to Si nanowires studied by ballistic electron emission microscopy (BEEM)

BEEM is a hot-electron (HE) technique based on scanning tunneling microscopy that can probe buried metal/semiconductor and metal/dielectric interfaces with nm-scale spatial resolution and energy resolution of a few meV. BEEM is a three-terminal technique, so the HE energy and interface electric field can be varied independently. I will discuss two studies of interest for future transistor technologies. The first concerns the band structure and alignments in a 20 nm-thick film of the high-k dielectric material Sc$_{2}$O$_{3}$ grown epitaxially on Si(111). Sc$_{2}$O$_{3}$ and related rare-earth/transition metal oxide films on Si were found to have similar band alignments and bandgap, and also ``tailing'' conduction band (CB) states extending $\sim $1 eV below the primary CB. We combined BEEM with internal photoemission to measure the band alignment and to study electron transport through these ``tail'' states.\footnote{W. Cai, S. E. Stone, J. P. Pelz, L. F. Edge, and D. G. Schlom, Appl. Phys. Lett \textbf{91}, 042901 (2007).} Surprisingly, these tail states were found to form a robust band of extended states that supports elastic hot-electron transport even \textit{against} an applied electric field. The second study concerns HE injection and transport through ``end-on'' metal contacts made to $\sim $100 nm diameter vertical Si nanowires (NWs) embedded in a SiO$_{2}$ dielectric. At low HE flux, We observed \textit{lateral variations} of the local Schottky Barrier Height (SBH) across individual end-on Au Schottky contacts, with the SBH at the contact edge found to be $\sim $25 meV lower than at the contact center. Finite-element electrostatic simulations suggest that this is due to a larger interface electric field at the contact edge due to positively charged Si/native-oxide interface states near the Au/NW contact, with this (equilibrium) interface state charge induced by local band bending due to the high work function Au contact. We also observed a strong \textit{suppression} of the hot-electron transmission efficiency at larger HE flux, likely due to (non-equilibrium) \textit{steady-state negative charge accumulation} in metastable traps at the Si/oxide interface located near the injecting metal contact. Ongoing BEEM measurements of metal contacts to SrTiO$_{3}$ substrates and films may also be discussed.\\[4pt] In collaboration with W. Cai, Y. Che, L. F. Edge, D. G. Schlom, E. R. Hemesath, and L. J. Lauhon.   

Metropolis Prize Talk: Defects in Al$_{2}$O$_{3}$ and their impact on III-V/Al$_{2}$O$_{3}$ MOS-based devices

As the dimensions of conventional silicon devices continue to shrink, novel approaches are required to achieve increasing performance demands. Recently Intel announced the implementation of a 3-D MOSFET geometry known as the tri-gate transistor for their 22 nm technology. In addition to different geometries, new materials will also be needed for future technologies. In this talk, we will consider the use of III-V channel materials, and novel gate dielectrics. Al$_{2}$O$_{3}$ is a promising dielectric for III-V devices. However, the presence of deep levels and fixed charge in the Al$_{2}$O$_{3}$ layer is a concern, with native defects being a potential source of traps, leakage, and fixed charge. We will present the results of hybrid density functional calculations for such defects. The energetic positions of defect-induced levels will be discussed in the context of the III-V/ Al$_{2}$O$_{3}$ interface. We find that native defects are a source of border traps, and fixed charge in the dielectric. We will also discuss the interaction of hydrogen with such defects, in the context of passivation. Our results indicate that hydrogen is effective at removing border traps, and helps to alleviate the problem of fixed charge. This work was performed in collaboration with A. Janotti and C. G. Van de Walle.   

Charge Traps at and near High-K Oxide/III-V Interfaces

The effort to achieve higher performance metal-oxide-semiconductor (MOS) devices prompts interest in new semiconductor channel materials such as indium gallium arsenide that can achieve larger drive currents than state-of-the-art Si field effect transistors, at low operating voltages. In order for InGaAs-channel transistors to approach their performance limits, however, high permittivity (high-k) metal oxide gate dielectrics must be prepared on the III-V surface in a manner that produces a minimal areal density of charge-trapping defects. This presentation will review different experimental approaches to prepare relatively passive interfaces between deposited oxides and GaAs or InGaAs. Both pre-oxide deposition and post-deposition methods will be summarized. It will also describe the influence of near-interface defects in the oxides (border traps) and why these particular defects are so significant for arsenide MOS devices. An attempt will be made to associate electrically-active traps detected at different energies in the III-V semiconductor bandgap with specific surface and point defects, based on prior reported experimental and computational observations. The difficulty of quantifying trap densities using typical capacitance-voltage and conductance-voltage methods developed for silicon MOS will be discussed.   

Electrical characterization of interfacial defects

Aggressive transistor scaling to achieve better chip functionality calls for the introduction of new dielectric and metal materials into traditional device gate stacks. The advanced gate stacks represent multilayer structures, the materials of which may strongly interact (primarily during high temperature processing), generating structural defects in these layers. These complex structures pose new challenges in interpreting electrical measurements, which are sensitive to even extremely small concentrations of electrically active defects. The critical task is, thus, to link the structural and electrical characteristics of these multicomponent gate stacks in order to identify and control defects affecting device performance. In this presentation, we focus on analyzing interfacial defects affecting electrical characteristics of the metal/high-k (HK) gate stacks, which are of major interest to the semiconductor industry. We first developed models of the physical processes governing the measurements of the electrical techniques we used that allowed us to extract the structural parameters of the defects from the electrical data. By comparing the extracted parameters to those obtained by ab initio calculations of the material structures, we identified the nature of the contributing defects. A recently proposed model for random telegraph noise (RTN) and frequency-dependent charge pumping (CP) measurements that takes into consideration the multi-phonon lattice relaxation induced by charge trapping/detrapping at the defect sites was employed to extract characteristics of the traps in the interfacial SiO2 layer in HfO2-based HK devices. Our results indicate that the electron capture/emission times are controlled by the lattice re-arrangement (caused by the trapped electrons) rather than by electron tunneling to/from the trap as generally assumed. The strong dependency of the measured values on defect relaxation and ionization energies allows these values to be extracted; the values can then be used as a defect identifier. Complementary modeling of the gate leakage current in HK devices during electrical stress using the same approach yields characteristics of the traps in the interfacial SiO2 layer contributing to trap-assisted tunneling (TAT). Based on the values obtained by RTN, CP, and TAT measurements, the electrically active defects were tentatively assigned to oxygen vacancies in various charged states. In all cases, stress-induced traps were generated exclusively in the interfacial layer of the HK stacks, consistent with earlier findings that HK dielectrics are more resistant to defect generation than SiO2. Based on these findings, as well as an earlier TEM/EELS study of the elemental composition of the breakdown path, we proposed that the breakdown path formation/evolution in the interfacial layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries in the overlaying high-k film. This model successfully describes the temperature-dependent evolution of interfacial layer degradation through various breakdown phases.