Bulletin of the American Physical Society
2006 APS March Meeting
Monday–Friday, March 13–17, 2006; Baltimore, MD
Session U7: Nanoscale Pattern Generation and Lithography |
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Sponsoring Units: FIAP Chair: Ya-Hong Xie, University of California, Los Angeles Room: Baltimore Convention Center 307 |
Thursday, March 16, 2006 8:00AM - 8:36AM |
U7.00001: Extreme Ultraviolet Lithography Invited Speaker: // [Preview Abstract] |
Thursday, March 16, 2006 8:36AM - 9:12AM |
U7.00002: Maskless Electron-beam and Optical Lithography Invited Speaker: Mask-based lithography is ideal for high-volume manufacturing because it enables enormous data transfer rates. In manufacturing, the high cost of masks and lithography tools can be amortized over large numbers of products. However, for low-volume manufacturing, research and the exploration of novel applications of lithography, maskless lithography systems have significant cost and convenience advantages. Scanning-electron-beam lithography (SEBL) systems are widely used in research and some low-volume manufacturing. They suffer from well known problems of pattern-placement accuracy, slow writing speed and, in some cases, substrate damage. Strategies for circumventing these problems will be described. A maskless optical-lithography system, called zone-plate-array lithography (ZPAL), has recently been demonstrated that achieves high throughput by the parallel operation of 1000 diffractive-optical lenses [www.lumarray.com]. The performance of ZPAL will be described and compared to SEBL. Also, novel nonlinear strategies for pushing the resolution of ZPAL to feature sizes comparable to those achieved by SEBL will be described. [Preview Abstract] |
Thursday, March 16, 2006 9:12AM - 9:48AM |
U7.00003: Ion Beam Patterning at the Nanometer Scale Invited Speaker: Due to the absence of diffraction limitations, the extensive available process parameter space, and the prospects for one-shot imposition of a projection-reduced master mask pattern, ion beam patterning appears to offer a viable path to large-scale manufacturing of devices and systems based on nanoscale features, while offering robustness, flexibility, high quality of image definition and high throughput. We will review a variety of process variables, and the strategies by which they can be optimized for a specific application, in terms of resolution of the smallest features, minimal proximity effects, minimal edge effects, minimal statistical noise, high dimensional stability and pattern registration, and minimal effects on underlying layers. We use SRIM and other simulations of ion interactions to model the effects of ion species, energy, fluence and beam current density, and their impact on the choice of mask structure and type of photoresist where appropriate. We consider the application of the ions to pattern photoresist layers, or to locally modify the topography of polymer films, or to locally activate surfaces for selective adsorption. We also consider options for in-situ growth of 3D nanoscale features. Direct modification of the interfaces of thin film structures, and local ballistic disordering will also be discussed. Experimental demonstrations of low energy ion beam patterning with $<$40 nm resolution will include contact mask patterning of thin films of various polymers, and patterning of high-anisotropy magnetic multilayers for high storage density disk drive applications. [Preview Abstract] |
Thursday, March 16, 2006 9:48AM - 10:24AM |
U7.00004: Atomic Image Projection Electron Beam Lithography Invited Speaker: While we are approaching to the nanotechnology era, as was proposed by Richard Feynman in 1959, our main concern still lies in how one can controllably manufacture and utilize nanometer scale features. The top-down approaches, most notably, lithography based techniques still have the problem of throughput although it has been successfully demonstrate to make features with the size less than 10 nm. The bottom-up approaches, either utilizing chemical vapor deposition process to make carbon nanotube or wet-chemical process to make size controllable quantum dots and rods, still have the limitation of extending it to many different types of materials and also delivering them on a wafer size substrate to make nanodevices. In this talk, we will propose a novel electron beam lithography technique to make nanometer scale features. The novelty of this process lies in the fact that one can utilize the crystalline lattice image commonly observed by the high resolution transmission electron microscopy as an ultimate mask to generate nanometer scale patterns. Using this technique, we demonstrate that down to 45 nm pitch size can be resolved on hydrogen silsesquioxine (HSQ) e-beam resist material. The patterns are formed on Si substarte with the dot size of about 30 nm and the line size of about 25 nm. This technique can be extend to define less than 10 nm size features only if the suitable resist is developed. [Preview Abstract] |
Thursday, March 16, 2006 10:24AM - 11:00AM |
U7.00005: Diblock Copolymers for Nanoscale Patterning Invited Speaker: As the size scale of device features becomes increasingly smaller, conventional lithographic processes become increasingly more difficult and expensive, especially at a minimum feature size of less than 50 nm. Consequently, to achieve higher density circuits, storage devices or displays, it is evident that alternative routes need to be developed to circumvent both cost and manufacturing issues. An ideal process would be compatible with existing technological processes/manufacturing techniques and these strategies, together with novel materials, could allow significant advances to be made in meeting both short-term and long-term demands for higher density and faster devices. The self-assembly of block copolymers (BCP), two polymer chains covalently linked together at one end, provides a robust solution to these challenges. As thin films, immiscible BCP self-assemble into a range of highly-ordered morphologies where with size scale of the features is limited to the size of the polymers chains and are, therefore, nanoscopic in size. While self-assembly alone is sufficient for a number of applications in fabricating advanced microelectronics, directed self-orienting self-assembly processes are also required to produce complex devices with the required density and addressability of elements to meet future demands. By combining tailored self-assembly processes, a bottom-up approach, with micro-fabrication processes, a top-down approach, the ever-present thirst of the consumer for faster, better and cheaper devices can be met in very simple, yet robust, ways. [Preview Abstract] |
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