Bulletin of the American Physical Society
75th Annual Gaseous Electronics Conference
Volume 67, Number 9
Monday–Friday, October 3–7, 2022;
Sendai International Center, Sendai, Japan
The session times in this program are intended for Japan Standard Time zone in Tokyo, Japan (GMT+9)
Session GF2: Plasmas for Energy Applications
10:00 AM–12:00 PM,
Friday, October 7, 2022
Sendai International Center
Room: Shirakashi 2
Chair: Ahmad Hamdan, University de Montreal
Abstract: GF2.00005 : A Mask-free and Contactless Patterned Plasma Processing Technique for Interdigitated Back Contact Silicon Heterojunction Solar Cells Fabrication*
11:00 AM–11:15 AM
Presenter:
Erik Johnson
(LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris)
Authors:
Junkang WANG
(LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris)
Pavel Bulkin
(LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris)
Monalisa Ghosh
(LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris)
Dmitri Daineka
(LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris)
Pere Roca i Cabarrocas
(LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris)
Sergej Filonovich
(TotalEnergies OneTech)
José Alvarez
(Laboratoire de Génie Electrique et Electronique de Paris, CNRS, CentraleSupélec, Université Paris-Saclay)
Erik Johnson
(LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris)
To circumvent the complex fabrication process, we present a novel mask-free and contactless method to form those interdigitated patterns by a PECVD process. It involves using a slotted powered RF electrode, with parallel slits in it, in a CCP-PECVD chamber. By keeping the two electrodes in close proximity, plasma will selectively light only within the slits, thus mimicking the patterns on the electrode [2]. Deploying this patterned plasma process with an NF3/Ar etching gas mixture on a well-designed silicon thin film stack, the interdigitated patterns required for IBC architectures are obtained.
Multiple characterizations are performed along the process flow to give guidance for the processes optimization. J(V) characteristics of the resulting PV devices will be presented, and the importance of an additional step to remove the “damaged” layer on the surface (in the trench) left by the patterned etching process will be discussed.
*The authors acknowledge the financial support of Total and the ANR through the PISTOL Industrial Chair Project (ANR‐17‐CHIN‐0002‐01).
Follow Us |
Engage
Become an APS Member |
My APS
Renew Membership |
Information for |
About APSThe American Physical Society (APS) is a non-profit membership organization working to advance the knowledge of physics. |
© 2024 American Physical Society
| All rights reserved | Terms of Use
| Contact Us
Headquarters
1 Physics Ellipse, College Park, MD 20740-3844
(301) 209-3200
Editorial Office
100 Motor Pkwy, Suite 110, Hauppauge, NY 11788
(631) 591-4000
Office of Public Affairs
529 14th St NW, Suite 1050, Washington, D.C. 20045-2001
(202) 662-8700