Demonstrating an erasure-detected entangling gate between dual-rail cavity qubits - part 2

Dual-rail qubits encoded in 3D superconducting cavities are a promising approach for realizing error-detected qubits [1]. Detecting errors on physical qubits allows them to be converted to erasure errors, dramatically easing the task of quantum error correction and improving near-term error-detected algorithms. To this end, it is crucial to be able to detect hardware errors, even when they occur during the qubit operations themselves. This has been achieved for most of the required operations such as state-preparation and measurement [2], single qubit gates [3, 4], and erasure-checks [5].  

In part 2 of this talk, we focus on the implementation of the remaining ingredient, a parametrizable entangling ZZ-gate [6], on our hardware. We describe the gate tune-up procedure and characterize both the error-detected gate fidelity and erasure rate. Our results show the dominant errors occur at the few percent level and are detected with high efficiency, leaving us with highly suppressed gate infidelities when no errors are flagged. These early demonstrations show dual-rail cavity qubits maintain the desired properties of erasure qubits during all necessary qubit operations, including the two-qubit gate. 

[1] Teoh et al., PNAS 120 (41), e2221736120, 2023

[2] Chou et al., arXiv:2307.03169, 2023

[3] Lu, Maiti et al., Nat Comm 14, 5767, 2023

[4] Chapman, de Graaf et al., PRX Quantum 4, 020355, 2023

[5] Koottandavida, Tsioutsios et al. in prep.

[6] Tsunoda, Teoh et al., PRX Quantum 4, 020354, 2023