Bulletin of the American Physical Society
APS March Meeting 2022
Volume 67, Number 3
Monday–Friday, March 14–18, 2022; Chicago
Session D39: Semiconductor Qubits IIFocus Session Recordings Available
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Sponsoring Units: DQI DCMP Chair: Mark Gyure, UCLA Room: McCormick Place W-196A |
Monday, March 14, 2022 3:00PM - 3:36PM |
D39.00001: Material and integration challenges for large-scale silicon quantum computing Invited Speaker: Maud Vinet
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Monday, March 14, 2022 3:36PM - 3:48PM |
D39.00002: Electron g-factor renormalization in SiGe superlattice quantum wells Benjamin D Woods, Emily S Joseph, Thomas W McJunkin, Yi Feng, Donald E Savage, Max G Lagally, Susan N Coppersmith, Mark Eriksson, Mark G Friesen, Robert J Joynt An electron g-factor of g ~ 1.6 has been observed in a SiGe superlattice quantum well with a periodic Ge concentration ranging from 0% to 9% within a supercell of length L ~ 1.8 nm. This shift from go = 2 represents a g-factor renormalization one to two orders of magnitude larger than what may be naively expected based on the material composition of the quantum well. We present a model that attributes this strong renormalization to the coupling of the conduction band minima to states with strong spin-orbit coupling. More specifically, the periodic potential arising from the Ge concentration oscillations couples the conduction band minima near the X-point to states near the zone center of the Brillouin zone. In contrast to the conduction band minima, which have a spectral weight dominated by pz orbitals, the states near the Brillouin zone center have significant contributions from all three p orbital species, which gives rise to strong spin-orbit coupling and g-factor renormalization. This g-factor renormalization may be useful in manipulation of qubit spin resonance without the use of micromagnets. |
Monday, March 14, 2022 3:48PM - 4:00PM |
D39.00003: Anomalous g-factor in a Si/SiGe heterostructure with oscillatory Ge concentration Emily S Joseph, Thomas W McJunkin, Benjamin D Woods, Benjamin Harpt, Yi Feng, Donald E Savage, Max G Lagally, Sue N Coppersmith, Mark G Friesen, Robert J Joynt, Mark A Eriksson We measure an electron g-factor of 1.6 in a quantum well consisting of predominately silicon with an oscillating varying concentration of Ge that oscillates in space between 0% and 9% with a period of 1.8 nm. This result is surprising, because bulk materials at all compositions of |
Monday, March 14, 2022 4:00PM - 4:12PM |
D39.00004: Increasing the valley splitting in Si/SiGe heterostructures by exploiting atomic concentration fluctuations Merritt P Losert, Brian Paquelet Wuetz, Sebastian Koelling, Lucas Stehouwer, Anne-Marije J Zwerver, Stephan G Philips, Mateusz T Madzik, Xiao Xue, Guoji Zheng, Mario Lodari, Sergey V Amitonov, Nodar Samkharadze, Amir Sammak, Lieven Vanderspyen, Rajib Rahman, Sue N Coppersmith, Oussama Moutanabbir, Mark G Friesen, Giordano Scappucci We present a theory of how alloy disorder affects the intervalley coupling and valley splitting in quantum dot qubits in Si/SiGe heterostructures. We show that this theory is in good agreement with experiments as well as the NEMO-3D 20-band strain-dependent sp3d5s* tight-binding model. We find that, for realistic devices, alloy disorder is the dominant source of variation in the valley splitting. Moreover, we show that increasing the alloy disorder increases the spread of the intervalley coupling, thereby increasing the average valley splitting. These results lead to a new and counterintuitive strategy for engineering quantum wells with large average valley splittings: increasing the alloy disorder. We find that adding just 5% Ge to the bottom of the quantum well enhances valley splittings substantially, achieving splittings larger than 100 μeV over 95% of the time. This strategy runs counter to the prevailing strategy of making devices with little disorder and very sharp interfaces. |
Monday, March 14, 2022 4:12PM - 4:24PM |
D39.00005: Cryogen-free scanning gate microscope for the characterization of Si/Si0.7Ge0.3 quantum devices at milli-Kelvin temperatures Seongwoo Oh, Artem Denisov, Pengcheng Chen, Jason R Petta The conduction band of bulk Si exhibits a six-fold valley degeneracy, which may adversely impact the performance of silicon quantum devices [1]. The spatial characterization of valley states in Si remains limited; especially in functional quantum devices. We describe here a cryogen-free scanning gate microscope for the characterization of Si/Si0.7Ge0.3 quantum devices at mK temperatures. The microscope is based on the Pan-walker design, with coarse positioning piezo stacks and a fine scanning piezo tube [2]. To reduce the pulse tube noise, we utilize both active and passive vibration isolation mechanisms, and achieve a root-mean-square noise in z of ∼ 2 nm [3]. As a proof of concept, we use the microscope to manipulate the charge occupation of a Si quantum dot, opening up a range of possibilities for the exploration of quantum devices and materials |
Monday, March 14, 2022 4:24PM - 4:36PM |
D39.00006: Scanning-gate-driven photon assisted tunneling in a Si/Si0.7Ge0.3 double quantum dot Artem Denisov, Jason R Petta, Seongwoo Oh, Pengcheng Chen, Gordian Fuchs |
Monday, March 14, 2022 4:36PM - 4:48PM |
D39.00007: Simulating electron densities obtained in scanning gate microscopy of Si/SiGe quantum dot devices Gordian Fuchs, Artem Denisov, Chris R Anderson, Mark F Gyure, Fabio Ansaloni, Jason R Petta Silicon-based quantum devices are a serious contender for scalable quantum computing, enabling coherent and highly controllable semiconductor spin qubits [1]. However, the six-fold “valley-degeneracy” of bulk Si [2] poses a challenge to silicon-based spin qubits [3]. Progress in understanding what limits valley splitting has been limited by the lack of high throughput measurements, calling for the development of new measurement techniques. A cryogen-free scanning gate microscope (SGM), compatible with Si/Si0.7Ge0.3 quantum dot devices and operating at milli-Kelvin temperatures, was recently demonstrated [4]. The microscope has the potential to enable spatial mapping of the valley splitting in silicon-based quantum dot devices. Here, we report recent efforts on quantum dot device simulations to investigate the influence of the tip bias in a SGM on the electronic occupation of a Si/SiGe quantum dot. |
Monday, March 14, 2022 4:48PM - 5:00PM |
D39.00008: Reduced Disorder and Opportunities for Scalable, 2-Dimensional Gate Array Design Using the SLEDGE Architecture in Si/SiGe Exchange-Only Qubits Michael Jura The recently-demonstrated Single-Layer Etch-Defined Gate-Electrode (SLEDGE) architecture in Si/SiGe exchange-only qubits enables flexible device design and fabrication by separating the front-end-of-line (FEOL) gate stack from the back-end-of-line (BEOL) interconnects [1]. For FEOL gates, moving from a lift-off to subtractive fabrication process with improved gate stack cleans decreases electrostatic disorder; we measure Hall bars with a reduced minimum electron density at which conduction occurs and quantum dot device gates with reduced variability in voltages at which electrons load and tunnel. BEOL routing enables scalable, 2-dimensional gate array designs of the FEOL, instead of 1-dimensional arrays or ring-like designs, but requires good electrical connections between vias and gates. We show that if a via is poorly-connected to a gate, the gate behaves as an unwanted quantum dot (coined “parasitic metal dot,” PMD). With design and fabrication improvements, we measure drastically reduced PMD prevalence. We further show SLEDGE devices can be used for coherent operation of high-performance qubits. |
Monday, March 14, 2022 5:00PM - 5:12PM |
D39.00009: 28Si/SiGe heterostructures with engineered semiconductor/dielectric interface Davide Degli Esposti, Brian Paquelet Wuetz, Viviana Fezzi, Mario Lodari, Amir Sammak, Giordano Scappucci Advancing the materials science of quantum information devices plays an essential role in the pursuit of larger spin-based quantum processors with more functionality. Previously, we demonstrated 28Si/SiGe heterostructures that hosted quantum processors with two-qubit gate fidelities above 99\% [1][2]. We build on these results and present 28Si/SiGe heterostructures with an engineered semiconductor/dielectric interface to reduce remote impurities and improve device uniformity on a wafer scale. We characterize the heterostructures by magnetotransport and show a two-fold reduction of the standard deviation for key transport metrics such as peak mobility, percolation density, and quantum lifetime. We correlate the results of quantum transport with studies of charge noise in quantum dots fabricated on the same heterostructures. |
Monday, March 14, 2022 5:12PM - 5:24PM |
D39.00010: Quantitative strain mapping in Si0.7Ge0.3/Si/ Si0.7Ge0.3 heterostructures for spin qubits Cedric Corley-Wiciak, Carsten Richter, Wolfgang M Klesse, Eduardo Zatterin, Tobias Schuelli, Agnieszka A Corley-Wiciak, Ignatii Zaitsev, Costanza L Manganelli, Giovanni Capellini, Michele Virgilio, Wolfram Langheinrich, Ketan Anand, Yuji Yamamoto, Marvin H Zoellner, Malte Neul, Lars R Schreiber, Inga Seidler, Ran Xue, Yujia Liu We present laterally resolved maps of the lattice strains around spin qubits housed in Si/SiGe heterostructures and demonstrate that that material related inhomogeneities must be taken into account in the optimization and design for scaled CMOS-compatible quantum processors. |
Monday, March 14, 2022 5:24PM - 5:36PM |
D39.00011: Roughness of Si/SiO2 interface and its impact on CMOS spin qubits Jesus D Cifuentes Pardo Quantum computing has the potential to be world changing due to its promise to tackle problems currently intractable to even the most advanced present day supercomputer. The leading technology uses superconducting transmon qubits with an overall effective qubit count of 53. However, a 1-million-plus physical qubit processor is required to make quantum computers useful for the most notable applications. To achieve this, scalability and operating temperature may well become a significant challenge for superconducting qubits. On the other hand, silicon qubits, which are much smaller than transmons and able to work at higher temperatures [1,2] emerge as a viable candidate for large-scale quantum processing. The prospect of leveraging the multi-trillion dollar complementary-MOS (CMOS) manufacturing industry is a very strong motivator for the development of silicon-CMOS-based quantum computing. However, it remains unknown what will be the impact of the defects on the oxide layer in CMOS devices that are fabricated to host quantum dots spin qubits. In this talk we will explore how the roughness in the Si/SiO2 interface impacts silicon-based CMOS qubits by utilising atomistic multiband tight-binding for single electron quantum dots and path integral Monte Carlo (PIMC) for electron interactions. [1] C. H. Yang et al., Nature 580, 505 (2020). [2] L. Petit et al., Nature 580, 355 (2020). |
Monday, March 14, 2022 5:36PM - 5:48PM |
D39.00012: Observation of disorder-induced decoherence for individual electron spins in moving quantum dots Baptiste Jadot, Martin Nurizzo, Pierre-André Mortemousque, Emmanuel Chanrion, David J Niegemann, Vivien Thiney, Arne Ludwig, Andreas D Wieck, Christopher Bäuerle, Matias Urdampilleta, Tristan Meunier Controlled electron displacement has been identified as one possible strategy to convey on-chip quantum information in semiconductor quantum circuits. Understanding the mechanisms limiting the transfer fidelity is therefore an important task to validate this quantum information conveyer procedure. |
Monday, March 14, 2022 5:48PM - 6:00PM |
D39.00013: Quantum-well subband-degeneracy refrigeration with cascaded cryogenic solid-state heat pumps Chulin Wang, Thomas Douglas, Matthew Grayson Design for a solid-state heat pump to eventually replace dilution refrigerators is introduced based on the cyclic adiabatic expansion and compression of 2D electron gas subbands to achieve sub-Kelvin temperatures. With the one-shot version proposed by Rego & Kirczenow (APL, 1999), the proposed device cools by a factor of TC/TH = g1/g2 by decreasing the electric field in the quantum well via gates to increase the subband occupancy from g1 to g2. Narrow “throttle” gates to the left and right of the compression/expansion gates can selectively deplete a narrow strip of electrons, which electrically and thermally isolate the central electron reservoir alternately from the heat sink and from the cold load. Optimal materials selection and device design is supported by an analytical model of device function. A 1 cm2 single-stage device is predicted to cool to 0.85 K with a 1 K heat sink and 1 MHz cycle frequency. Moreover, temperatures below 0.10 K can be achieved by a multi-stage cascaded device. Future generations of this device are intended to eventually supplant dilution refrigerators for cooling of solid-state quantum computers. |
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