Micro-architecture of quantum information processor using planer packaging*

Of the many potential hardware platforms, superconducting quantum circuits have become the leading contender for constructing a scalable quantum computing system. Not only have we seen significant advances in recent years in reliable fabrication and control technology, but the quality of the qubits themselves have increased by many orders of magnitude. Almost current architecture designs necessitate a two-dimensional arrangement of superconducting qubits with nearest-neighbor interactions, that is compatible with powerful quantum error-correction using the surface code.

The current consensus within the field is that control wiring for such chips should be fabricated in the third dimension, utilizing several techniques to place bias, readout and control wires orthogonal to the plane of the chip itself. This technique has shown much promises, but it is also very unclear and still a significant engineering challenge if these intricate, three-dimensional wiring and packaging technology are compatible with maintaining high fidelity operations and increasing chip size.

In this talk, we present a revolutionary new large-scale micro-architecture that completely side-steps this issue. The proposed pseudo-2D architecture of superconducting qubits can be constructed in a physical bi-linear arrangement of superconducting qubits and allows for each physical qubit to be biased, measured and controlled using wiring that remains in-plane with the chip (eliminating completely the need for 3D control line fabrication and packaging). Utilizing the micro-architecture, we also show how a large Raussendorf cluster can be produced, which realizes the cluster state model of surface code quantum error correction. Moreover, we propose that other transformed arrangement can generate a 3D-cluster-state on completely planer circuit with some overhead.