Time-domain Multiplexing and Optimization of Gate-based Sensing for Silicon-based Quantum Devices

In the quest for scaling up silicon-based quantum computing, readout by already existingvgate electrodes has gained prominence due to its reduced impact in the qubit layout and comparable sensitivities to conventional charge sensors. Recently, single-shot spin readout has been achieved with this technique [1-3] but further improvements are necessary, first, to meet the fidelity thresholds and timescales needed for the implementation of fast feedback in error correction protocols and, secondly, to be able to scale the method.
In this talk, I will first present the steps we have taken to reduce the measurement timescales of gate-based sensors beyond the state-of-the-art using silicon CMOS systems and off-chip superconducting technology. By combining the large gate lever arm of CMOS devices with high Q electrical resonators [4] and Josephson parametric amplification in the 600 MHz range, we reduce the integration time required to read the state of a silicon double quantum dot below the thresholds for fault-tolerant readout [5].
Secondly, I will present a strategy based on time-domain multiplexing to scale gate-based sensing. Here, we interfaced a single electrical resonator to two silicon quantum devices via digital transistors at milikelvin temperatures to demonstrate the building blocks of a dynamic random access architecture for efficient readout of complex quantum circuits. Our results demonstrate a path to reducing the number of resonators required to read large arrays of devices and facilitate scaling.

References
[1] A. West, et al. Nat Nano 14 437 (2019)
[2] P. Pakkiam, et al. PRX 8 041032 (2018)
[3] G. Zheng et al., Nat Nano 14 742 (2019)
[4] I. Ahmed, et al. Phys. Rev. App. 10, 014018 (2018).
[5] Schaal et al. Phys Rev Lett 124 067701 (2020)
[6] Schaal et al. Nat Elect 2 236 (2019)