Bulletin of the American Physical Society
APS March Meeting 2020
Volume 65, Number 1
Monday–Friday, March 2–6, 2020; Denver, Colorado
Session J17: Focus Silicon Spin Qubits in Double Quantum DotsFocus

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Sponsoring Units: DQI Chair: Susan Clark, Sandia National Laboratories Room: 203 
Tuesday, March 3, 2020 2:30PM  3:06PM 
J17.00001: Si based quantum computer architecture and associated engineering challenges Invited Speaker: Maud Vinet Sibased QC appears as a promising approach to build a quantum processor; thanks to the size of the qubits, the quality of the quantum gates and the VLSI ability to fabricate billions of closely identical objects. The quality of Si spin qubits has improved very fast with the introduction of isotopically purified 28Si. 
Tuesday, March 3, 2020 3:06PM  3:18PM 
J17.00002: A Valley HotSpot Driven SingletTriplet Qubit in a Silicon MOS DQD Ryan Jock, Noah T Jacobson, Martin Rudolph, Dan R. Ward, Malcolm S. Carroll, Dwight R Luhman Electron spins in silicon quantum dots (QDs) have gained traction as a promising qubit platform due to the controllability of qubitqubit interactions and the availability of mature silicon microelectronics fabrication techniques. However, confining electrons to QDs at the Si/SiO_{2} interface has recently been shown to produce stronger than expected spinorbit (SO) physics. Here, we present a novel operating mode of a singlettriplet qubit that exploits an intervalley SO interaction to drive highorthogonality, electricalonly qubit control. We employ this interaction to produce a highperformance qubit with operational ST_{0} rotation frequencies exceeding 200 MHz and a quality factor, Q = f x T_{2}^{*}, near 20. Utilizing SO effects to drive qubits offers the advantage of allelectrical control, avoiding the need for micromagnets or onchip microwave striplines, and allows for a characterization of the MOS platform without the added fabrication complexity of additional nanofabricated metal layers. 
Tuesday, March 3, 2020 3:18PM  3:30PM 
J17.00003: Learning the states of double quantum dot systems: A raybased approach Justyna Zwolak, Thomas McJunkin, Sandesh Kalantre, Samuel Neyens, Evan R MacQuarrie, Lisa F Edge, Mark Alan Eriksson, Jacob Taylor Given the progress in the construction of multiquantum dot (QD) arrays in both 1D and 2D [1,2], it is imperative to replace the current practice of manual tuning to a desirable electronic configuration with a standardized and automated method. Recently, we have experimentally realized an autotuning paradigm proposed by Kalantre et al. [3] that combines machine learning (ML) and optimization routines, with ConvNets used to characterize the state and charge configuration of single and double QD states from measurements via the conductance of a nearby charge sensor [4]. Now we expand on this work and propose a novel approach where we use 1D traces (“rays”) measured in multiple directions in the gate voltage space to describe the position of the features characterizing each state (i.e., to “fingerprint” the state space). Using these “fingerprints” instead of fullsized 2D scans we train an ML algorithm to differentiate between various state configurations. Here, we report the performance of the raybased learning on experimental data and compare it with our imagebased approach. 
Tuesday, March 3, 2020 3:30PM  3:42PM 
J17.00004: Spin shuttling in a silicon double quantum dot Florian Ginzel, Adam Mills, Jason Petta, Guido Burkard Motivated by the demand[1] for long and intermediate range interaction in quantum information devices and recent developments[2,3] we theoretically analyze the dynamics of an electron during a detuning sweep in a silicon double quantum dot (DQD) occupied by one electron, and investigate possibilities and limitations of spin transport. Spinorbit interaction and an inhomogeneous magnetic field which can introduce errors are included in our model. Interactions that couple the position, spin and valley degrees of freedom open a number of avoided crossings in the spectrum allowing for diabatic transitions and interfering paths. The outcome of a spin shuttling protocol is explored by means of numerical simulations and an approximate analytical model based on the solution to the LandauZener problem. We find that constructive interference can ensure a high transport fidelity even for a fast protocol. Exploiting destructive interference between different paths the DQD can also act as a spin or valley filter. 
Tuesday, March 3, 2020 3:42PM  3:54PM 
J17.00005: Towards an electrically controlled spinvalley quantum dot qubit in silicon Nicholas Penthorn, John Rooney, Joshua S Schoenfield, Lisa F Edge, HongWen Jiang Electrical control of electron spins in semiconductor quantum dot qubits requires some form of spinelectric field interaction, typically as a micromagnetinduced field gradient. However, electron spins are known to couple to valley states in silicon [1], which could afford a new method for spin control without the need of a micromagnet or native spinorbit interaction. Building on our recent result of electrical control of a valley qubit in a Si/SiGe double quantum dot [2], we show that the valley splitting can be tuned by 32 μeV with modest voltages on local gates. Using realtime spin relaxation measurements on a single electron in this device with a variable external field, we see evidence of spinvalley mixing signified by a “hot spot” with high spin relaxation below 500 mT. Additionally, we show our progress on implementing valleymediated spin qubit operations. 
Tuesday, March 3, 2020 3:54PM  4:06PM 
J17.00006: Charge noise induced spin decoherence in a double quantum dot: Effects of a micromagnet Xinyu Zhao, Xuedong Hu Charge noise is one of the most important error sources for quantum gates in semiconductor systems. We study the decoherence of an electron spin in a double quantum dot in the presence of an inhomogeneous magnetic field. An exact dynamical equation is derived directly from the microscopic Hamiltonian, which allows us to investigate the impact of the nonMarkovian properties of the quantized bosonic environment. We show that nonMarkovian dynamics could cause a notable correction when measuring spin relaxation time. Our results reduce to the one predicted by the traditional Redfield master equation when BornMarkov approximation is applied. The spin relaxation and dephasing caused by the charge noise is suppressed by certain factors since the noise is indirectly (through the artificial spinorbit interaction from the micromagnet) coupled to spin. We show these factors strongly depend on the system parameters such as detuning, tunneling strength, field gradients in vertical or horizontal directions. Our results present a systematic approach to study decoherence processes caused by charge noise, particularly for quantum dots in an inhomogeneous magnetic field. 
Tuesday, March 3, 2020 4:06PM  4:18PM 
J17.00007: Universal quantum logic in hot silicon qubits Harmen Eenink, Luca Petit, Maximilian Russ, William I.L. Lawrie, Nico Hendrickx, Jim Clarke, Lieven M Vandersypen, Menno Veldhorst Large scale quantum computation can leverage significantly from semiconductor fabrication technology, to allow for quantum integrated circuits, hosting quantum hardware and control circuitry all on the same chip. However, leading qubit approaches operate at very low temperatures below 100 mK, where cooling power is extremely limited, and this severely impacts the perspective for practical quantum computation. Demonstrating qubit operation at elevated temperatures would therefore be a major breakthrough in the effort towards scalable quantum systems. 
Tuesday, March 3, 2020 4:18PM  4:30PM 
J17.00008: Intel Spin Qubits: Automated lowtemperature measurement and statistical data analysis for improved fabrication and device design Roman Caudillo, Florian Luthi, Lester Lampert, Thomas Watson, David J Michalak, Eric Henry, Payam Amin, Hubert C George, Stephanie Bojarski, Brennen Mueller, Ravi Pillarisetty, Jeanette Marie Roberts, Jim Clarke Spin qubits in silicon are in many ways similar to stateoftheart transistor devices, and they can both be manufactured with today’s 300mm equipment and processes. The 300mm fab infrastructure is a powerful tool because of its excellent process control that results in highquality devices with high reliability; however, it requires feedback from device performance grounded in statistical analysis of large data sets. Similarly, for quantum dots, automation and statistical data analysis of lowT measurements can be used to address challenges such as minimizing charge noise and TLS’s in dielectrics and other onchip materials, as well as eliminating spurious dots. Here we present an automated approach to tuning up quantum dots and extracting gate crosstalk, charging energy (E_{c}), leverarm, charge noise, and other device performance metrics, which are then fed back to device design and the fabrication process for iterative improvements in performance. Automation, and the large data sets that result, not only enable highthroughput measurements for rapid fabrication improvements, but also allow characterization of device limitations in new ways, including identifying regions of badness and the location of TLS’s, and ultimately will point the way toward highperformance qubits. 
Tuesday, March 3, 2020 4:30PM  4:42PM 
J17.00009: Intel Quantum Dot Devices: temperature dependence of electrical characteristics and correlating noise measurements for improved measurement turnaround Florian Luthi, Roman Caudillo, Thomas Watson, Lester Lampert, Otto Zietz, Hubert C George, Stephanie Bojarski, Brennen Mueller, Payam Amin, Eric Henry, David J Michalak, Ravi Pillarisetty, Jeanette Marie Roberts, Jim Clarke Quantum computing promises to tackle exciting and computationally difficult problems. Intel is leveraging 50 years of experience in semiconductor manufacturing to develop siliconbased spin qubits. One of the key challenges is the measurement bottleneck: Data acquisition at low temperatures (10 mK) is slow, and only few samples can be characterized per cooldown. Nonetheless, these measurements provide the ultimate feedback to device fabrication and design. At Intel, this problem is highlighted to the extreme: every week, thousands of SiMOS quantum dot devices are fabricated on 300 mm wafers, yet only a small fraction of these can be measured at mK temperatures. The need for lowtemperature electrical characterization can be reduced by understanding the temperature dependence of device data, enabling learning from measurements at elevated temperatures. Furthermore, correlations between directly relevant quantities (such as quantum dot charge noise) and device properties which are measured more quickly (such as pinchoff noise) are investigated. These quickturn monitors enable faster feedback to improve fab and pave the way to automated waferscale characterization of quantum dot devices at intermediate temperatures (24 K); this will help alleviate the measurement bottleneck. 
Tuesday, March 3, 2020 4:42PM  4:54PM 
J17.00010: Fabrication process and failure analysis for robust quantum dots in silicon John Dodson, Nathan Holman, Brandur Thorgrimsson, Samuel Neyens, Evan R MacQuarrie, Ryan H Foote, Thomas McJunkin, Lisa F Edge, Susan Nan Coppersmith, Mark Alan Eriksson We investigate several yield limiting steps in the fabrication of overlapping aluminum gate quantum dot devices in Si/SiGe. The thin, ~2 nm oxide that grows natively on aluminum and low thermal budget of aluminum devices presents a challenge for fabrication of quantum dot arrays with high yield. Gatetogate leakage from pinholing of the aluminum oxide, damage from electrostatic discharge (ESD), low breakdown voltages and gate geometry/morphology all present a significant risk of device failure in the active region. Additionally, dewetting of aluminum and formation of alloys during fabrication of interconnects from the active region of the device to the bond pads can result in failure of electrical signal transmission. We present lowtemperature oxidation techniques for a thicker aluminum oxide with breakdown voltages of over 4 volts, reducing the risk of damage due to ESD and gatetogate leakage. TEM images of overlapping gate structures identify failure modes stemming from gate geometry/morphology. Finally, we investigate the fabrication of interconnects between the active region and device bond pads to introduce thermal anneals into the fabrication process, prevent damage due to ESD, and to identify the maximum processing temperature at different stages of device fabrication. 
Tuesday, March 3, 2020 4:54PM  5:06PM 
J17.00011: Simplified MOS Quantum Dots for Materials Characterization Joshua Pomeroy, Aruna N Ramanayaka, Yanxue Hong, Ke Tang, Ryan Stein, Michael David Stewart Using singlelayer metal gate patterns, metaloxidesemiconductor (MOS) quantum dot devices with charge sensors are fabricated and measured as a simplified approach to developing more rigorous qualifying metrics than transport for materials and interfaces. Materials and interfaces are often identified as sources of charge traps and time instabilities difficult to assess with transport techniques, and the ability to form quantum dots and charge sense in these systems enables charge offset drift and, potentially, spin relaxation measurements to critically assess the feasibility of the materials and methods for use in qubit applications. Various multipledot designs with charge sensors have been fabricated, and the tunability and charge offset stability of these devices will be discussed in the context of developing tools for qualifying materials for quantum. 
Tuesday, March 3, 2020 5:06PM  5:18PM 
J17.00012: Development of simulator for silicon quantum dot devices based on semiclassical device modeling Hidehiro Asai, Shota Iizuka, Junichi Hattori, Tsutomu Ikegami, Koichi Fukuda, Takahiro Mori Recently, the novel design for qubit integration has been vigorously investigated for the realization of faulttolerant quantum computers and the noisy intermediatescale quantum (NISQ) technology. Silicon qubits have attracted much attention as a promising candidate for a building block of integrated quantum circuits because they can utilize cutting edge nanofabrication facilities for conventional logic devices. In order to develop the qubit suitable for largeintegrated quantum circuits and design whole picture of quantum circuits and its peripheral control circuits, the simulation tool for supporting the qubit design is strongly required, like technology computer aided design (TCAD) for conventional transistor design. In this presentation, we report our recent development of a prototype simulator which can simulate the basic characteristics of silicon quantum dot devices as a basis of spin qubit. We utilize semiclassical device simulation as solvers of Poisson equation and classical current continuity equation combined with newlydeveloped tunneling and Coulombblockade models to calculate transport in quantum dot devices. As a demonstration of the simulation, we are going to show calculation examples of charge stability diagrams for some quantum dot devices. 
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