Bulletin of the American Physical Society
APS March Meeting 2019
Volume 64, Number 2
Monday–Friday, March 4–8, 2019; Boston, Massachusetts
Session V26: Superconducting Qubits: Control Hardware and Methods |
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Sponsoring Units: DQI Chair: Baleegh Abdo, IBM Thomas J. Watson Research Center Room: BCEC 160B |
Thursday, March 7, 2019 2:30PM - 2:42PM |
V26.00001: Integration of classical electronics for quantum computing tasks in superconducting qubit systems Antonio Corcoles, Maika Takita, Ken Inoue, Scott Lekuch, Abhinav Kandala, Jay Gambetta, Jerry M. Chow The acts of controlling and measuring superconducting qubits for quantum information processing rely on classical electronic systems. Although metrics primarily associated to the quantum system, such as qubit coherence time and gate fidelity, are typically quoted as benchmarks for quantum processor quality, the integration of classical hardware and associated software with the quantum device plays a critical role both in these metrics and in the overall performance of a quantum computer. |
Thursday, March 7, 2019 2:42PM - 2:54PM |
V26.00002: Evaluating the performance of classical electronics for quantum computing tasks in superconducting qubit systems Maika Takita, Antonio Corcoles, Ken Inoue, Scott Lekuch, Abhinav Kandala, Jay Gambetta, Jerry M. Chow We present and discuss quantum protocols for near-term superconducting quantum processors for which quantum feedback or feedforward plays a key role. These protocols hinge heavily on classical electronics for qubit control and signal processing, which makes them ideal candidates for evaluating the performance of NISQ devices in the present and near future. We will discuss, in addition, ways in which these quantum protocols can be used for benchmarking systems exposed to errors that reach beyond quantum noise and coherent errors in qubit control. |
Thursday, March 7, 2019 2:54PM - 3:06PM |
V26.00003: Atomic flux pulses for a superconducting quantum processor, part 1: real-time corrections and repeatability of flux pulses Filip Malinowski, Michiel Adriaan Rol, Livio S Ciorciaro, Brian M Tarasinski, Yves Salathe, Niels Haandbaek, Jan Šedivý, Leonardo DiCarlo We present the calibration and characterization of atomic, repeatable flux pulses compatible with a flexible Quantum Instruction Set Architecture (QISA). The flux pulses take advantage of distortion corrections realized by real-time filtering in the arbitrary waveform generator as the sequence of pulses is executed, rather than conventional pre-distortion of the waveform shape in software. We combine the corrections with the net-zero waveform shape and quantify the repeatability of flux pulsing. The phases acquired by the qubit in each of two consecutive flux pulses match within 1 deg, independent of the delay between them. |
Thursday, March 7, 2019 3:06PM - 3:18PM |
V26.00004: Atomic flux pulses for a superconducting quantum processor, part 2: performance and benefits of net-zero conditional-phase gates Michiel Adriaan Rol, Filip K Malinowski, Francesco Battistel, Brian M Tarasinski, Barbara Terhal, Leonardo DiCarlo We use a novel pulse shape, named net-zero, to realize a coherence limited, codeword-triggered, and repeatable conditional-phase (CZ) gate between transmon qubits in a circuit QED processor. We characterize the performance of both conventional and net-zero CZ flux pulses and quantify specific error sources such as leakage, dephasing, relaxation, non-markovianity, and coherent errors. We compare experimental results to simulations that include realistic modeling of these effects. |
Thursday, March 7, 2019 3:18PM - 3:30PM |
V26.00005: Superconducting qubit control electronics - Part 1/2: system overview and control hardware Amit Vainsencher, Ben Chiaro, Roberto Collins, Brooks Foxen, Evan Jeffrey, Erik Lucero, Matthew McEwen, Daniel Sank, John M Martinis The need for numerous analog control lines presents a unique challenge in building control systems for large quantum processors. In the context of superconducting Josephson qubits, particular requirements for the control lines include phase matching across all channels, low noise, and minimal drift. In this talk, we discuss the design, implementation, and challenges encountered in building our next generation modular control system. Using this system in a configuration with 256 DACs, 84 IQ mixers, 24 ADC, and 16 microwave sources, we will show preliminary measurements on Bristlecone, our 72-qubit processor. |
Thursday, March 7, 2019 3:30PM - 3:42PM |
V26.00006: Superconducting qubit control electronics - Part 2/2: dispersive measurement Daniel Sank, Roberto Collins, Evan Jeffrey, Erik Lucero, Amit Vainsencher, Brooks Foxen, Ben Chiaro, John M Martinis Dispersive measurement of transmon-type qubits requires a microwave receiver with nearly 100 dB gain and ~100 mK system noise temperature. Recent increases in qubit number have introduced a new set of requirements on our receivers. These constraints include the need for smaller parts at cryogenic and room temperature stages, higher reliability, lower cost, and uniformity across multiple systems to ensure agreement between staging and production systems. In this talk, we discuss the design and implementation of our dispersive measurement system that meets our integration needs while maintaining performance, with particular focus on the room temperature electronics. We present preliminary results on our latest chips. |
Thursday, March 7, 2019 3:42PM - 3:54PM |
V26.00007: Superconducting Qubit Control with Single Flux Quantum Pulses in A Multichip Module: Part I – Fabrication and Pulse Driver Chuan-Hong Liu, Edward M Leonard, Matthew A Beck, Kenneth Dodge, Andrew L Ballard, Caleb Howington, Vito M Iaia, JJ Nelson, Alex Kirichenko, Daniel T Yohannes, Igor Vernik, Jason Walter, Oleksandr Chernyashevskyy, Oleg Mukhanov, Britton L Plourde, Robert F McDermott Superconducting qubits are an attractive candidate for quantum information. However, existing control techniques do not scale well to large-scale qubit arrays processing. A promising candidate for scalable control is the Single Flux Quantum (SFQ) digital logical family. In an initial implementation, the fidelity of SFQ-based qubit gates was limited by quasiparticle (QP) poisoning of the qubit induced by the dissipative SFQ pulse driver. Here we introduce a quantum-classical multichip module (MCM) where the SFQ driver and the qubit are segregated onto separate chips in order to suppress QP poisoning. We describe the design, fabrication, and thermalization of the MCM. Finally, we discuss the operation and characterization of the SFQ pulse generator and qubit. |
Thursday, March 7, 2019 3:54PM - 4:06PM |
V26.00008: Superconducting Qubit Control with Single Flux Quantum Pulses in A Multichip Module: Part II Qubit and Quasiparticle Measurement Kenneth Dodge, Andrew Ballard, Caleb Howington, Vito M Iaia, JJ Nelson, Chuan-Hong Liu, Edward M Leonard, Matthew A Beck, Alex Kirichenko, Daniel T Yohannes, Igor Vernik, Jason Walter, Oleksandr Chernyashevskyy, Oleg Mukhanov, Robert F McDermott, B.L.T. Plourde We demonstrate coupling of a Single Flux Quantum (SFQ) driver on a classical control chip to a superconducting qubit on a quantum chip in a multi-chip module package. A DC-SFQ driver on the classical chip emits quantized pulses that are capacitively coupled to the qubit island of a transmon on the quantum chip, allowing subharmonic driving of qubit rotations. We examine the effects of on- and off-resonant SFQ pulses on the state of the qubit and the response of the read-out cavity. Quasiparticle (QP) excitations created from the operation of the SFQ circuitry can be a source of decoherence and temporal instability in the qubit. QP contribution to the qubit admittance are examined by monitoring how relaxation and dephasing times correlate with QP creation. Mitigation strategies for QP poisoning will be discussed. |
Thursday, March 7, 2019 4:06PM - 4:18PM |
V26.00009: Reciprocal Quantum Logic Compatible SFQ-to-CMOS Amplifiers for High-Speed Data Transmission Elias Galan, Marie McLain, Micah Stoutimore, Andrew Miklich, Kurt Pleim, Ratz Paul, David McGuire, Oliver Oberg, Zachary Kyle Keane We have developed an amplifier for use in transmitting high-speed reciprocal quantum logic signals to CMOS digital circuitry at room temperature. The amplifier uses an integrated digital latch to convert the normally return-to-zero (RZ) format of a single flux quantum (SFQ) signal to non-return-to-zero (NRZ) format with a simple and space-efficient design. The NRZ format provides more signal power per unit bandwidth than RZ, and is easier to interface with CMOS circuitry. The output voltage is provided by a series of inductively isolated asymmetric DC superconducting quantum interference devices (SQUIDs). The power efficiency is estimated to be 32±9%. The DC SQUIDs are designed in-line with a 50 Ohm transmission line to reduce high frequency oscillation and improve output signal integrity. Experimentally, the output amplifier demonstrated a bit error rate of better than 9.5E-8 at 1 Gb/s; extrapolations to the optimal operating point project a bit error rate of 1E-37. |
Thursday, March 7, 2019 4:18PM - 4:30PM |
V26.00010: Engineering cryogenic setups for 100-qubit scale superconducting circuit systems Sebastian Krinner, Simon Storz, Philipp Kurpiers, Paul Magnard, Johannes Heinsoo, Raphael Keller, Janis Luetolf, Christopher Eichler, Andreas Wallraff A robust cryogenic infrastructure in form of a wired, thermally optimized dilution refrigerator is essential for solid-state based quantum processors. In this talk, we present a cryogenic setup, which minimizes passive and active heat loads, while guaranteeing rapid qubit control and readout. We review design criteria for qubit drive lines, flux lines, and output lines used in typical experiments with superconducting circuits. The passive heat load of stainless steel and NbTi coaxial cables and the active load due to signal dissipation are measured, validating our robust and extensible concept for thermal anchoring of attenuators, cables, and other microwave components. Our results are important for managing the heat budget of future large-scale quantum computers based on superconducting circuits. |
Thursday, March 7, 2019 4:30PM - 4:42PM |
V26.00011: Scalable instrumentation for general purpose quantum computers Glenn Jones, Deanna Abrams, Stephan Brown, Lauren Capelluto, Schuyler Fried, Sabrina Hong, Blake Johnson, Rob Lion, Adam Mocarski, Mike Pelstring, Chad Rigetti, Damon Russell, Michael Rust, Colm Ryan, Diego Scarabelli, Rodney Sinclair, Prasahnt Sivarajah, Chloe Song, Alexa N Staley, John Stevenson, Mark Suska, Nima Taie-Nobarie, Celena Tanguay, Nikolas Tezak, Stefan Turkowski As quantum computers grow to increasing numbers of qubits, it becomes advantageous to use specialized or customized hardware to generate the microwave pulses that control the qubits. We present an FPGA-based system for controlling qubits that demonstrates a number of advantages over commercially available test equipment. The system has been optimized to minimize the noise sources to which the qubits are most susceptible, enabling high fidelity quantum gates. The overall architecture is designed to support hybrid quantum-classical algorithms. Optimized processor cores control the microwave signal generation and provide arbitrary control flow, allowing gates to be applied conditioned on a measurement result. Gate parameters, such as rotation angle, can also be dynamically computed, or loaded from classical shared memory, and applied in real-time. We present results from a straightforward usage of this capability: actively resetting a qubit to its ground state. |
Thursday, March 7, 2019 4:42PM - 4:54PM |
V26.00012: Scaling the input/output architecture of quantum processors to kQbit, and beyond, size in the NISQ era Daan Kuitenbrouwer, Wouter Bos, Kiefer Vermeulen, Kelvin Lindeborg, Riemer Sorgedrager, Vivien Thiney, Jakob Kammhuber, Sal Bosman Most quantum computing hardware architectures combine the requirements of individually addressable qubits and cryogenic temperatures of the quantum processor. This combination makes the design of the interface between the quantum processor and its classical backend a critical element in the scalability of the architecture of the quantum computer. Todays coaxial cabling solution becomes (at best) impractical for processors beyond the kQbit regime, due to its unwanted resonances, form-factor, costs and thermal load. Moreover the non-uniformity of the individual lines complicates the operation and control of the quantum processor by its classical back-end. Here we discuss an input/output (i/o) system for scalable quantum computers that uses a monolithic multi-layer flexible circuit from room temperature to ~10 miliKelvin to interface the quantum processor with its room temperature electronics. Important aspects like thermal properties, signal transmission and conditioning by integrated filtering, and cross-talk are reviewed for the various approaches to quantum computing. Also the required modularity and inter-operability of the cryogenic hardware and interface to the quantum processor are considered. |
Thursday, March 7, 2019 4:54PM - 5:06PM |
V26.00013: Optimizing readout hardware for large scale quantum computers Theodore White, Ben Chiaro, Brooks Foxen, John M Martinis In a superconducting quantum computer, each microwave readout line requires low noise parametric amplifiers, circulators, and filters. These are expensive resources, not only in cost but also in weight and size. In larger systems it is increasingly necessary to use frequency multiplexed readout tones such that many qubits can be measured with a single line. This in turn requires superconducting parametric amplifiers that operate with broad bandwidth and high saturation power, while maintaining near quantum limited noise performance. In this talk we will compare several different varieties of amplifier from the perspective of device performance, fabrication difficulty, yield, and wiring complexity. We will also report on performance metrics for these architectures in our superconducting qubit processors. |
Thursday, March 7, 2019 5:06PM - 5:18PM |
V26.00014: Scalable FPGA-based qubit control hardware Gang Huang, Yilun Xu, Lawrence Doolittle, Unpil Baek, Irfan Siddiqi As quantum computing technology evolves from research laboratories to potential industrial applications, the scalability and synchronization of classical control hardware becomes a limiting factor in the development of intermediate-scale (50-100) qubit systems. We introduce a novel FPGA-based architecture comprised of multiple qubit control boards, interconnected by a fiber-based synchronization system, to implement basic operations such as qubit control and readout. Our hardware represents a cost-effective alternative to commercial test and measurement style AWGs and detectors, and can be readily scaled up for intermediate-scale quantum processors with low latency and synchronization among all channels to a common clock cycle. Having assembled a prototype system with commercial evaluation boards, we present results from bench testing of the hardware and initial tests demonstrating qubit control. Customized hardware with higher channel density is under development. |
Thursday, March 7, 2019 5:18PM - 5:30PM |
V26.00015: An FPGA-based quantum feedback system for real-time qubit control Unpil Baek, Yilun Xu, Gang Huang, Lawrence Doolittle, Irfan Siddiqi Measurement-based quantum feedback is highly sought after due to its potential for quantum error correction and preserving quantum coherence. However, measurement-based quantum feedback has been difficult to achieve due to the limited lifetime of qubits as compared to the longer time required for readout and feedback signal processing. We present a new FPGA-based qubit control architecture that integrates the qubit readout, state recognition, and feedback response together to minimize latency. Using our initial hardware, we demonstrate real-time quantum feedback on superconducting qubits and apply this technology to a multi-qubit superconducting quantum processor. |
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