Hardware Considerations for High-connectivity Quantum Annealers*

Quantum annealing is an optimization technique which could potentially make use of quantum tunneling to enhance performance. Existing quantum annealers implement pairwise interactions between qubits, with each qubit coupling to up to six others on a “Chimera” connectivity graph. This hardware graph can be used to embed complex optimization problems, but with significant overhead in energy scale and problem size. Here, we investigate an approach to designing quantum annealers with a higher degree of hardware connectivity. In particular, we discuss coupler chains and parallel couplers, the basic building blocks of a proposed coupler tree architecture.