Session B32: Field Effect Devices from 2D Materials

Electron transport and device physics in monolayer transition-metal dichalcogenides

Two-dimensional transition-metal dichalcogenides (TMDs) represent a promising class of materials for electronic and photonic devices, benefiting from their sizable bandgap of 1-2eV and ultrathin body. However, one of the major issues is that the experimental mobility is much lower than the theoretical phonon limit. It is speculated that the mobility is degraded by many extrinsic factors. In this talk I will present our systematic investigations on the electron transport and field-effect transistors of monolayer TMDs (including MoS$_{\mathrm{2}}$ and WS$_{\mathrm{2}})$. We find that the major extrinsic mobility limiting factors are charged impurities, traps and point defects. We develop a facile low-temperature thiol chemistry to repair the sulfur vacancies and improve the interface quality, resulting in significant reduction of the charged impurities and traps. In combination with high-k dielectrics that further screens the charged impurities, we are able to achieve record-high room-temperature mobilities of \textasciitilde 150cm$^{\mathrm{2}}$/Vs and 83cm$^{\mathrm{2}}$/Vs for monolayer MoS$_{\mathrm{2}}$ and WS$_{\mathrm{2}}$, repectively. We further develop a theoretical model to quantitatively correlate these extrinsic scattering sources to measured electrical data. Our study shows that interface engineering is critical for high-performance transistors based on 2D semiconductors. \begin{enumerate} \item []References \item Hao Qiu, Lijia Pan, Zongni Yao, Junjie Li, Yi Shi* and Xinran Wang*, \textit{Appl. Phys. Lett.}, 100, 123104 (2012). \item Hao Qiu, Tao Xu, Zilu Wang, Wei Ren, Haiyan Nan, Zhenhua Ni, Qian Chen, Shijun Yuan, Feng Miao, Fengqi Song, Gen Long, Yi Shi, Litao Sun, Jinlan Wang* {\&} Xinran Wang*, \textit{Nature Comm.} 4, 2642 (2013). \item Zhihao Yu, Yiming Pan, Yuting Shen, Zilu Wang, Zhun-Yong Ong, Tao Xu, Run Xin, Lijia Pan, Baigeng Wang, Litao Sun, Jinlan Wang, Gang Zhang, Yongwei Zhang, Yi Shi* {\&} Xinran Wang*\textit{, Nature Comm. 5, 5290 (2014)}. \item Yang Cui, Run Xin, Zhihao Yu, Yiming Pan, Zhun-Yong Ong, Xiaoxu Wei, Junzhuan Wang, Haiyan Nan, Zhenhua Ni, Yun Wu, Tangsheng Chen, Yi Shi*, Baigeng Wang, Gang Zhang*, Yong-Wei Zhang {\&} Xinran Wang*, \textit{Adv. Mater. 27, 5230 (2015)}. \item Zhihao Yu, Zhun-Yong Ong, Yiming Pan, Yang Cui, Run Xin, Yi Shi*, Baigeng Wang, Yong-Wei Zhang, Gang Zhang* {\&} Xinran Wang*, \textit{Adv. Mater. 28, 547 }(2016). \end{enumerate}   

Reconfigurable WSe$_{\mathrm{2}}$ device: three fundamental devices in one.

Moore's law has, for several decades, governed the transistor scaling and has brought about the technological revolution for better, faster and more efficient devices. However, with the advent of 7nm node, scaling is fast reaching the fundamental material limits, and the need for alternative technologies has never been more pressing. Until recently, most of the efforts have focused on finding alternative channel materials as a direct replacement for Si. Here, we propose an alternative to scaling by completely redesigning the way logic functions are implemented. We report a single multifunctional device fabricated in two-dimensional WSe$_{\mathrm{2}}$ using electrostatic doping that can reconfigure into the three fundamental building blocks of modern electronics: the p-n diode, the metal-oxide-semiconductor field effect transistor, and the bipolar junction transistor. To characterize their properties, we use a single material parameter, the interface density of states, to describe the key figure-of-merit of all three devices.   

Fabrication and Characterization of Epitaxial Graphene Field Effect Transistors

We report on planar transistors using epitaxial graphene grown both on the (0001) and the (000-1) face of semi-insulating 4H-SiC, following the work reported by Kunc et al.\footnote{J. Kunc et al. \textbf{Nano Lett.} 14, 5170-5175 (2014)} Epitaxial graphene on SiC is of high quality and holds a high potential for graphene electronics. We use Raman spectroscopy, atomic force microscopy and transport measurements (Current-voltage under various gate voltage) as a function of temperature to investigate the properties of the material and to characterize the devices. On the carbon face (000-1), a 2D Electron Gas (2DEG) is formed between a surface silicate and the SiC bulk after thermal annealing. Multilayer epitaxial graphene (MEG) is used to contact this 2D conduction layer, forming a 1D junction. Results are analyzed in terms of 1D Schottky barrier between the MEG and the 2DEG. The gated structure exhibits on/off ratio up to $5 \times 10^6$ at room temperature. Various types of junction structures can also be produced on Si face (0001) of SiC, that involve single layer and structured graphene.   

Scalable Production of Sensor Arrays Based on High-Mobility Hybrid Graphene Field Effect Transistors

We have developed a scalable fabrication process for the production of DNA biosensors based on gold nanoparticle-decorated graphene field effect transistors (AuNP-Gr-FETs), where monodisperse AuNPs are created through physical vapor deposition followed by thermal annealing. The FETs are created in a four-probe configuration, using an optimized bilayer photolithography process that yields chemically clean devices, as confirmed by XPS and AFM, with high carrier mobility (3590 cm$^{\mathrm{2}}$/V\textbullet s) and low unintended doping (Dirac voltages of 9.4V). The AuNP-Gr-FETs were readily functionalized with thiolated probe DNA to yield DNA biosensors with a detection limit of 1 nM and high specificity against noncomplementary DNA. Our work provides a pathway toward the scalable fabrication of high-performance AuNP-Gr-FET devices for label-free nucleic acid testing in a realistic clinical setting.   

High performance unipolar MoTe$_{\mathrm{2}}$ field effect transistors enabled by doping and Al$_{\mathrm{2}}$O$_{\mathrm{3}}$ capping $_{\mathrm{\thinspace }}$

We carry out the first systematic experiment on carrier type modulation of MoTe$_{\mathrm{2}}$ FET in this work. unipolar p- and n-type MoTe$_{\mathrm{2}}$ FETs with 10$^{\mathrm{5}}$ and 10$^{\mathrm{6}}$ on-off ratios are achieved through rapid thermal annealing (RTA) and Benzyl Viologen (BV) doping respectively. By varying the vacuum level in RTA chamber before annealing and BV dopant concentration, annealing condition, both hole and electron doping concentration can be modulated in a wide range from slight doping to degenerate like doping. Furthermore, Al$_{\mathrm{2}}$O$_{\mathrm{3}}$ is deposited onto the device surfaces for the mobility engineering. Hole and electron mobilities are improved to 62 cm$^{\mathrm{2}}$/Vs and 82 cm$^{\mathrm{2}}$/Vs respectively after Al$_{\mathrm{2}}$O$_{\mathrm{3}}$ capping; they are among the highest carrier mobilities of MoTe$_{\mathrm{2}}$ transistors ever obtained. A lateral homogeneous MoTe$_{\mathrm{2}}$ p-n diode is fabricated combining the electron and hole doping techniques, the device displays excellent diode properties with a high rectification ratio of 10$^{\mathrm{4}}$ at 0 gate bias and an ideality factor of 1.2.   

Facile Fabrication of Graphene/MoS$_{\mathrm{2}}$ Heterostructure Devices on Arbitrary Substrates by Photolithography.

Atomically thin materials like graphene and transition metal dichalcogenides are ideal candidates to create ultra-thin electronics that is suitable for flexible substrates. However, high-yield and mass production of these heterostructures is a challenge. We developed a process to fabricate devices based on heterostructures of two-dimensional materials grown by CVD, using standard photolithography. We showed that the transfer and patterning processes do not degrade the structural integrity and the optical properties of the two-dimensional materials. Devices fabricated from CVD-grown graphene and MoS$_{\mathrm{2}}$ yield photoresponsivity higher than 800 AW$^{\mathrm{-1}}$ to 633nm laser, with no gate applied. This excellent performance is comparable or above photodetectors made with exfoliated flakes and electron-beam lithography, making this method very promising for large-scale optoelectronics applications.   

Modulation of surface flatness and van der Waals bonding of two-dimensional materials to reduce contact resistance.

Despite that the novel quantum mechanical properties of two-dimension (2D) materials are well explored theoretically, their electronic performance is limited by the contact resistance of the metallic interface$^{\mathrm{1}}$ and therefore their inherent novel properties are rarely realized experimentally. In this study, we demonstrate that we can largely reduce the contact resistance induced between metal and 2D materials, by controlling the surface condition of 2D materials, eg. surface flatness and van der Waals bonding. To induce the number of more effective carrier conducting modes, we engineer the surface roughness and dangling bonds of the 2D interface in contact with metal. As a result, electrical contact resistance of the metal interface is significantly reduced and carrier mobility in the device level is enhanced correspondingly. [1] D. W. Yue, C. H. Ra, X. C. Liu, D. Y. Lee and W. J. Yoo, \textit{Nanoscale}, 2015, \textbf{\textit{7}}, 825-831   

Engineering MoS2 contact by inserting an ultrathin tunnelling barrier

Semiconductor transition metal dichalcogenides (TMDs) are 2D semiconductors that host attractive transport properties such as unconventional quantum Hall effect and spin-valley physics. However, metal contacts typically result in a Schottky barrier, making it difficult to access fundamental properties of the intrinsic charge transport. In this report, we utilize an ultrathin tunneling layer into the contact interface to achieve ohmic contact to MoS$_2$ monolayer and bilayer. We are able to reduce Schottky barrier height down to 10 meV and get a linear I-V response down to 1.7 K with low contact resistance. This tunneling structure does not rely on low work function metals and phase engineered MoS$_2$, which makes it promising in practical application.   

Dielectric Integration in Transition Metal Dichalcogenides Field-Effect Transistors

Dielectric plays a crucial role for the scattering of charge carriers two-dimensional transition metal dichalcogenides (TMDs) field-effect transistor channels. The role of various sources of scattering originating from the substrate and the channel/substrate interface such as charged impurities, charge traps, surface roughness, and remote surface optical phonons could be equally important for device performance. On the other hand, miniaturization of device causes the short channel effect. Using high-k dielectric is the proposed solution in this direction but the challenges of high-k dielectric synthesis/growth are important problems to fabricate scalable devices in future electronics. In this work, we will discuss the unique method for the synthesis of high--k dielectric and TMDs field-effect transistor fabrication {\&} characterization by using prepared dielectric.   

Passivation and Depassivation of Defects in Graphene-based field-effect transistors

Field effect transistors based on graphene on amorphous SiO$_{\mathrm{2}}$ substrates were fabricated, both with and without a top oxide passivation layer of Al$_{\mathrm{2}}$O$_{\mathrm{3}}$. Initial I-V characteristics of these devices show that the Fermi energy occurs below the Dirac point in graphene (i.e. p-type behavior). Introduction of environmental stresses, e.g. baking the devices, causes a shift in the Fermi energy relative to the Dirac point. 1/f noise measurements indicate the presence of charge trapping defects. In order to find the origins of this behavior, we construct atomistic models of the substrate/graphene interface and the graphene/oxide passivation layer interface. Using density functional theory, we investigate the role that the introduction and removal of hydrogen and hydroxide passivants has on the electronic structure of the graphene layer as well as the relative energetics for these processes to occur in order to gain insights into the experimental results.   

Graphene-on-GaN Hot Electron Transistor

Hot electron transistors (HETs) are promising devices for potential high-frequency operation that currently CMOS cannot provide. In an HET, carrier transport is due to the injection of hot electrons from an emitter to a collector which is modulated by a base electrode. Therefore, ultra-thin base electrodes are needed to facilitate ultra-short transit time and high performance for THz operation range. In this regard, graphene, the thinnest conductive membrane in nature, is considered the best candidate for the base material in HETs. The existing HETs with SiO$_{\mathrm{2}}$/Si as emitter stack suffer from low current gain and output current density. In this work, we use the two-dimensional electron gas (2-DEG) in a GaN-based heterostructure as emitter and monolayer graphene as the base electrode. The transport study of the proof-of-concept device shows high output current density (\textgreater 50 A/cm$^{\mathrm{2}})$, current gain (\textgreater 3) and ballistic injection efficiency of 75{\%}. These results indicate that performance parameters can be further improved by engineering the band offset of the graphene/collector stack and improved interface between graphene and GaN.   

Large contact noise in graphene field-effect transistors

Fluctuations in the electrical resistance at the interface of atomically thin materials and metals, or the contact noise, can adversely affect the device performance but remains largely unexplored. We have investigated contact noise in graphene field effect transistors of varying device geometry and contact configuration, with channel carrier mobility ranging from 5,000 to 80,000 cm$^{2}$V$^{-1}$s$^{-1}$. A phenomenological model developed for contact noise due to current crowding for two dimensional conductors, shows a dominant contact contribution to the measured resistance noise in all graphene field effect transistors when measured in the two-probe or invasive four probe configurations, and surprisingly, also in nearly noninvasive four probe (Hall bar) configuration in the high mobility devices. We identify the fluctuating electrostatic environment of the metal-channel interface as the major source of contact noise, which could be generic to two dimensional material-based electronic devices. arXiv:1611.01181.   

Fermi level pinning of Monolayer Molybdenum Dichalcogenides.

Electrical metal contacts to two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDCs) are considered as main bottleneck to the device performance due to weak metal dependences with high contact resistances (Rc), stubborn polarities and high Schottky barrier heights (SBH), indicating strong Fermi level pinning. Here, we demonstrate the first experimental results about Fermi level pinning of monolayer MoS2 and monolayer MoTe2. From our results, we quantitatively compared with theoretical calculations, in terms of the pinning factor and charge neutrality level of monolayer TMDCs. The pinning factors S were found to be 0.11 and -0.07 for monolayer MoS2 and MoTe2 respectively. These suggest much stronger Fermi level pinning effect and lower SBH than theoretical prediction. Our results further implies that metal work functions can be much weakly influential to contact properties on practical devices, overridden by the effect of defects.