Session W16: Focus Session: Graphene Electronic Devices II

Extrinsic and Intrinsic Charge Trapping at the Graphene/Ferroelectric Interface

In previous works on graphene ferroelectric field effect transistors (GFeFETs), the characteristics of the devices were found to be largely affected by ``anti-hysteresis'' associated with charge trapping instead of ferroelectric domain switching. In this work, with PbTiO$_3$/SrTiO$_3$ (PTO/STO) superlattices, the effect of surface adsorbates was largely diminished by tuning the transition temperature of superlattices and depositing exfoliated graphene at an elevated temperature. With the removal of such extrinsic charge traps, the impact from the ``intrinsic'' defects of the ferroelectric substrate was revealed, inducing fast ($\sim$10 $\mu$s) charge-trapping and remaining active even at cryogenic temperatures. The defects manifested themselves as unit-cell deep square pits, which were evident from contact-mode Atomic Force Microscopy (AFM) of the interface. An asymmetry in electron and hole trapping was observed. Optimized superlattice growth conditions minimized the surface defects and subdued the charge trapping associated with it. The result was a robust, ramping speed independent, room temperature ferroelectric switching in GFeFETs. With an ideal interface, the work was further extended to study graphene transport across potential barriers/junctions.   

Sub-harmonic gap structure and Magneto-transport in suspended graphene --Superconductor ballistic junctions

Inducing superconductivity in graphene via the proximity effect enables to study the rich transport of the massless Dirac fermions at the Superconductor(S) - Graphene (G) interface. Some of the predictions are pseudo diffusive transport in Ballistic SGS junctions at low carrier densities and the unique specular and retro Andreev reflections in graphene. One of the challenges in observing these experimentally is to fabricate highly transparent ballistic SGS junctions that can be probed at low carrier densities near the Dirac point. In this talk we will present our recent results on suspended graphene- Niobium Josephson weak links. Our devices exhibit a mobility of $\sim$ 350000 cm$^{\mathrm{2}}$V$^{\mathrm{-1}}$s$^{\mathrm{-1}}$ with a carrier density as low as 10$^{\mathrm{9}}$ cm$^{\mathrm{-2}}$. Below the Superconducting transition temperature (T$_{\mathrm{c}})$ $\sim$ 9K, the devices show supercurrent and sub-harmonic gap structure due to Multiple Andreev reflections. In the vicinity of the Dirac point, the sub-harmonic gap structure becomes more pronounced, which as predicated, is indicative of pseudo-diffusive transport. With a fine scanning of gate voltage close to Dirac point we see emergence of some unusual sub- gap structures. We also report on our study of these samples below the upper critical field of Nb ($\sim$ 3.5T), where superconducting proximity effect coexists with Quantum Hall effect.   

Ultra-Short Channel Graphene Devices

Measurements and modeling of ultra-short nano-electronic devices consisting of metallic electrodes and graphene channels are presented. We will discuss the novel formation and characterization of these devices. The short channel of the devices permits the observation of high-field effects. This includes current saturation that has relevance to future size-scaling of atomically-thin nano-electronics in the sub-10 nm regime. Unusual features in the current- voltage characteristics are explained by an analytical ballistic model. In addition, we investigate the effect of contact induced energy level broadening of the electrodes and contact resistance on the current saturation.   

Ab initio simulation and design of graphene-based transistors at the atomic scale

Two-dimensional materials, such as graphene and molybdenum disulfide, have attracted much attention because of their unique properties. Graphene's high mobility make it a very promising material for next generation electronics, but its zero band gap is a big hurdle for digital transistors. However, graphene nanoribbons can exhibit band gaps due to quantum confinement, and their electronic properties differ depending on the structures of their edges. Based on the real space multigrid method and the non-equilibrium Green functions technique for multi-probe systems, we have developed massively parallel DFT-based software to calculate quantum transport properties with several thousands atoms. We present results for transport properties of graphene-based transistors with different atomic structures and study the effects of nanoribbon length, width and gate structure.   

Low-Resistance Spin Filtering from Ferromagnet-Graphene-Ferromagnet Junctions

Nickel-graphene interfaces have been recently demonstrated to habor spin polarizations of up to 42{\%} with Ni/Graphene/MgO/Co heterostructures exhibiting negative out-of-plane magnetoresistances of 31{\%} [1]. These experiments agree qualitatively with theoretical predictions of spin filtering at planar Ni-Graphene and Co-Graphene interfaces [2]. We previously demonstrated room temperature magnetoresistance in vertical NiFe-Graphene-Co junctions [3]. Now we have fabricated high-quality NiFe(111)-Graphene-Co and NiFe(111)-Graphene-Fe junctions grown in-situ that exhibit high MR at room temperature while maintaining a very low interface resistance. Such junctions embody an excellent source of spin-polarized current for spintronics applications like fast and non-volatile magnetic random access memory. \\[4pt] [1] Martin et al., ACS Nano 8 (8), 7890, 2014.\\[0pt] [2] Karpan et al., Phys. Rev. Lett. 99, 176602, 2007\\[0pt [3] Cobas et al., Nano Letters 12, 3000, 2012.   

Plasma enhanced atomic layer deposition of ultrathin oxides on graphene

Graphene, a single atomic layer of sp2 bonded carbon atoms, possesses extreme material properties that point toward a plethora of potential electronic applications. Many of these possibilities require the combination of graphene with dielectric materials such as metal oxides. Simultaneously, there is interest in new physical properties that emerge when traditionally three dimensional materials are constrained to ultrathin layers. For both of these objectives, we explore deposition of ultrathin oxide layers on graphene. In this project, we perform plasma enhanced atomic layer deposition (PEALD) of aluminum oxide on graphene that has been grown by chemical vapor deposition atop copper foil and achieve oxide layers that are \textless 1.5 nm. Because exposure to oxygen plasma can cause the graphene to deteriorate, we explore techniques to mitigate this effect and optimize the PEALD process. Following deposition, the graphene and oxide films are transferred to arbitrary substrates for further analysis. We use x-ray photoelectron spectroscopy, Raman spectroscopy, and atomic force microscopy to assess the quality of the resulting films.   

Energy gap formation and gap states analysis in bilayer graphene

The targeted issue for bilayer graphene is low $I_{\mathrm{on}}$/$I_{\mathrm{off}}$ at the room temperature, which is explained by the variable range hopping in ?gap states?. However, there will be intrinsically no interface states in bilayer graphene because there is no dangling bonds, compared with P$_{\mathrm{b}}$ centers in SiO$_{\mathrm{2}}$/Si system. The origin for the gap states is still open question. In spite of this, the detailed measurements on $D_{\mathrm{it}}$ and time constant for gap states have not been reported yet. One of reasons could be the leakage current through the top gate insulator since robust methodology is not established. Here, we demonstrates a considerable suppression of the low-field leakage in bilayer graphene by applying the high-pressure O$_{\mathrm{2}}$ annealing to Y$_{\mathrm{2}}$O$_{\mathrm{3}}$ top gate insulator. The reliable Y$_{\mathrm{2}}$O$_{\mathrm{3}}$ top gate insulator provides the access to the carrier response issue in the largely-opened band gap. In this talk, we focus on the conductance measurements for bilayer graphene to extract $D_{\mathrm{it}}$ and time constant. Based on these measurements, two possible origins for the gap states, (i) border traps at the edge of Y$_{\mathrm{2}}$O$_{\mathrm{3}}$ and (ii) the local breakdown of A-B stacking in bilayer graphene, are discussed.   

SrO(001) on graphene: a universal buffer layer for integration of complex oxides

We report the successful growth of high-quality crystalline SrO on highly-ordered pyrolytic graphite (HOPG) and single layer graphene by molecular beam epitaxy. The epitaxial SrO layers have (001) orientation as confirmed by x-ray diffraction (XRD), and atomic force microscopy measurements show rms surface roughness of optimal films to be 1.2 {\AA}. Transport measurements of exfoliated graphene after SrO deposition show a strong dependence between the Dirac point and Sr oxidation. To show the utility of SrO as a buffer layer for complex oxide integration, we grew perovskite crystal SrTiO$_{\mathrm{3}}$ on SrO, and it was also confirmed to have (001) orientation from x-ray diffraction. This materials advancement opens the door to integration of many other complex oxides to explore novel correlated electron physics in graphene.   

Building a Better Barristor -- The Case for Carbon Nanotubes over Graphene

A dilute carbon nanotube (CNT) network is used as a field-transparent, gate-tunable, source electrode in a nanotube/silicon Schottky barrier field effect transistor -- a barristor [1]. Analogous to the graphene barristor, the gate-field modulates the Fermi-level of the low density-of-states CNT source electrode, thus controlling the barrier height at the junction. Unique to the CNT device, however, is the ability of the gate field to penetrate through the porous regions of the dilute CNT network to tune the carrier density in the semiconductor, thus also controlling the width of the depletion layer near the interface [2]. This phenomena was first described in 2008 using an organic semiconductor channel layer in the carbon nanotube enabled, vertical, field effect transistor (CN-VFET) [3]. Here we shift our focus to high-mobility, inorganic, semiconductors to demonstrate a silicon-based CN-VFET. Unlike the bottom-gate, organic CN-VFET, our present device features a top-gate structure for which a two-step, low-temperature atomic layer deposition process enabled the growth of a high-k dielectric layer on top of the low surface energy CNT network. Operating the device in reverse bias yields on-current densities exceeding 100A/cm$^{\mathrm{2}}$ at a drive voltage of 5V with on/off ratio over 10$^{\mathrm{7}}$, suitable for a wide range of microelectronic power and logic applications. [1] Y. Heejun \textit{et al.} \textit{Science} 2012. 336, 1140, [2] M. G. Lemaitre \textit{et al}. \textit{ACS Nano}, 2012, 6, 9095, [3] Liu, B, \textit{et al}. \textit{Adv. Mat.} 2008. 20,. 3605   

Electronic transport in graphene structure: from weak to strong localization regimes

Graphene, often named the wonder material for its many fascinating properties, has sparked out intense research activities over the last decade. Electronic transport in graphene became rapidly an important research field because of the early reported extremely high charge carrier mobility which triggered large expectations for nanoelectronic devices. Besides mobilities, graphene samples can exhibit particularly long electronic coherence lengths which allow for phase-related quantum transport phenomena such as the weak and strong localization transport regimes. This makes graphene a remarkable playground for fundamental studies of localization theory in low-dimensional systems. In this presentation, using tight-binding models enriched by first principle calculations, and a real-space Kubo-Greenwood method, multiscale simulations of the electronic transport in various graphene-based systems will be discussed. Such an approach allows for computing transport properties of systems containing millions of atoms reaching therefore the experimental sample size. In order to tailor graphene properties, chemical and/or structural modifications are widely used. However, such modifications act as scattering defects and usually deteriorate transport properties. Open a band gap while maintaining good mobility is a typical illustration of this dual problem. The influence of various chemical and structural defects will be analyzed. In particular, the consequences of unbalanced sublattice nitrogen doping in graphene and the case of highly defective graphene structures exhibiting strong Anderson insulator behaviors will be examined. Defects being even more detrimental for transport in 1D structures, a synthesis method that is free of defects is highly desirable. A solution is provided by a bottom-up chemistry approach where precursor monomers are self-assembled. The electronic transport and the potential for nanoelectronics of such defect-free carbon ribbons will also be discussed.   

Aharonov-Bohm interference in gate-defined ring of high-mobility graphene

Recent progress in preparing a high-quality graphene layer enables one to investigate the intrinsic carrier transport nature in the material. Here, we report the signature of conservation of the Berry's phase with preserved valley symmetry in Aharonov-Bohm (AB) interferometers fabricated on monolayer graphene with high carrier mobility, where the graphene was sandwiched between two thin hexagonal boron nitride (h-BN) layers. In measurements, charge carriers were confined in an AB ring-shaped potential well formed by the dual-gate operation of the bottom and top gates and the four-terminal magneto-conductance (MC) was measured with varying charge carrier density and temperature. Graphene in the device was in the ballistic regime as confirmed by the conductance quantization in steps of $\Delta G=$ 4$e^{2}$/$h$ in a constricted conducting channel of separate measurements. We observed h/e periodic modulation of MC and the zero-field conductance minimum with a negative MC background. The phase information of AB interference strongly suggests that carriers in the graphene in our devices preserve the intrinsic Dirac transport nature, which would be conveniently utilized for valleytronics in graphene.   

High-k Dielectric Nanosheets for Two-Dimensional material Electronics

Two-dimensional (2D) materials, such as graphene, hexagonal boron nitride (hBN), transition metal dichalcogenides, have shown great potential in nano-electronics because of their unique and superior physical properties. Among them, hBN has been known as an alternative dielectric that is atomically flat and free of trapped charges, which drastically enhance the mobility of graphene or MoS2. However, low dielectric constant (k $\sim$ 3.5) of hBN limits its use in transistors as gate lengths are scaled down to tens of nanometers. Here we demonstrate high performance graphene and MoS2 field effect transistors by using ultrathin Ca2NaNb4O13 nanosheet as a dielectric and mechanically stacking 2D materials. We developed a facile transfer strategy to build 2D materials devices based on the Ca2NaNb4O13 nanosheets. We measured and found that the oxide nanosheet has high dielectric strength, along with high dielectric constant at thickness of a few tens of nanometer. Therefore, multiple-stacked heterostructure of 2D materials shows high mobility at small operating voltage. This study shows possibility of high-k dielectric nanosheets for 2D electronics.