Bulletin of the American Physical Society
APS March Meeting 2015
Volume 60, Number 1
Monday–Friday, March 2–6, 2015; San Antonio, Texas
Session J19: Invited Session: Solutions to the Challenge of Post-CMOS Technology |
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Sponsoring Units: FIAP GMAG Chair: Matthew Copel, IBM Room: Mission Room 103B |
Tuesday, March 3, 2015 2:30PM - 3:06PM |
J19.00001: Prospects of III-V Tunnel FETs for Logic Applications Invited Speaker: Suman Datta In order to continue and maintain the pace of energy efficient transistor scaling, it is imperative to scale the supply voltage of operation concurrently. In this invited paper, we discuss a promising III-V device architecture such as III-V Heterojunction Tunnel FETs that may break the seemingly inflexible energy vs. performance limit of silicon CMOS transistors and provide high performance, low leakage and low operating voltage for future logic transistor technology. Unlike conventional MOSFETs, the Tunnel FET (TFET) architecture employs a gate modulated Zener tunnel junction at the source which controls the transistor ON and OFF states. This scheme fundamentally eliminates the high-energy tail present in the Fermi--Dirac distribution of the valence band electrons in the p$+$ source region and allows sub-kT/q steep slope device operation near the OFF state. This allows Tunnel FETs to achieve a much higher ION$-$IOFF ratio over a small gate voltage swing. A major challenge in the demonstration of high performance Tunnel FET is the limited rate of tunneling across the Zener junction which results in low drive current. Our results show, for the first time, that the on-current bottleneck in Tunnel FETs can be overcome by careful bandgap engineering. [Preview Abstract] |
Tuesday, March 3, 2015 3:06PM - 3:42PM |
J19.00002: mLogic: All Spin Logic Device and Circuits for Future Electronics Invited Speaker: Jimmy Zhu Utilizing Spin Hall Effect to drive domain wall motion for state-switching, mCell is a four terminal device with separate read/write paths. In a mCell, write path is a multilayer thin film stack of perpendicular anisotropy with a single domain wall trapped within. A read path consists of two laterally placed MTJs. An entire family of logic circuits, referred to as mLogic, can be configured solely using mCells without using any semiconductor transistors. In this talk, micromagnetic modeling and circuit simulations will be presented to show the technology potential. We will also present experimental fabrication of mCells and mLogic circuits. Kerr microscopy has been used to investigate current-driven domain wall motion in various magnetic multilayer structured read path. Electric testing of the fabricated mCell devices shows reliable state-switching of the mCells. [Preview Abstract] |
Tuesday, March 3, 2015 3:42PM - 4:18PM |
J19.00003: Spin-Torque Switching with the Giant Spin Hall Effect Invited Speaker: Daniel C. Ralph Magnetic devices are a leading contender for the implementation of memory and logic technologies that are non-volatile, that can scale to high density and high speed, and that do not wear out. However, widespread application of magnetic memory and logic devices will require the development of efficient mechanisms for reorienting their magnetization using the least possible current and power. I will discuss recent progress that has resulted from using the spin Hall effect in certain heavy metals to drive efficient magnetic switching. The spin Hall effect can provide spin-transfer torques that are more than an order of magnitude stronger per unit current than conventional spin torque in magnetic tunnel junctions. These torques can switch magnetic devices with either in-plane or perpendicular anisotropy, and can also drive very rapid domain wall motion in perpendicularly-magnetized samples. I will describe our efforts to identify the materials and device geometries that can provide the strongest spin Hall effects for applications, and to understand the physical mechanisms at work. This work was performed in collaboration with the research groups of Bob Buhrman at Cornell and Nitin Samarth at Penn State. [Preview Abstract] |
Tuesday, March 3, 2015 4:18PM - 4:54PM |
J19.00004: A Piezo-Electronic Solid-state Switch Capable of High Speed and Low Power Invited Speaker: Paul Solomon Society has witnessed an incredible digital revolution over the past half century starting with the integration of a few transistors in the 1960's. By shrinking the transistor (scaling) and reducing voltage simultaneously, numbers of transistors could be increased, and speed increased as well, without paying a penalty in terms of increased power. This free lunch continued for decades with huge increases in transistor number until today there are billions per chip with multi gigahertz clock rates. In the past decade the process of voltage reduction has come to an end because fundamental limits for field-effect transistors are being approached, and as a result power dissipation has soared. To continue down the scaling path a switch utilizing new physical principles is required, not subject to the same voltage limits. For this we proposed [1] a switch based on electro-mechanical transduction -- the Piezoelectronic Transistor (PET): An input voltage applied across a piezoelectric crystal causes a pressure wave which compresses a piezoresistive element resulting in a large change in its conductivity of several orders of magnitude. With this basic switch one can scale to lower voltages than the FET Furthermore, the stiff and short mechanical path permits multi-GHz speeds notwithstanding relatively slow acoustic velocities. In this talk we will explore the properties of the PET, the physics of its operation, analysis of its performance potential and applicability to future logic systems. In addition experimental results of our group toward realization of the PET will also be presented. \\[4pt] [1] Newns, D., Elmegreen, B., Liu, X-H {\&} Martyna, G. A . \textit{J. Appl. Phys.}, \textbf{111}, 084509 (2012). [Preview Abstract] |
Tuesday, March 3, 2015 4:54PM - 5:30PM |
J19.00005: Topological-insulator based field-effect transistors Invited Speaker: William Vandenberghe The edge states of topological insulators (TIs) have two attributes which are very desirable for classical computing field-effect transistor (FET) channel materials: a high electron mobility and robustness against defects and impurities. However, room temperature operation is required for practical FET applications and a mechanism to turn the device off is needed. We discuss how new hexagonal monolayer materials can provide us with room-temperature operation. We show how ribbons of these 2D TIs can be used to make a FET with a high on-current and a ratio between the on- and the off-state current exceeding three orders of magnitude. The high on-current enables high-speed operation while the small charge in the TI makes TI FETs interesting for low-power applications. [Preview Abstract] |
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