Session J7: Focus Session: Graphene Devices

Graphene-Superconductor based Bolometers

Due to its small volume and linear energy dependence of electron density of states, graphene has very low electronic heat capacitance compared to what is found in metals with achievable volume. This makes it a promising material for applications requiring bolometric sensing of radiation with a fast response without compromising sensitivity. Here we report fabrication of graphene-superconductor tunnel junctions and characterization of their bolometric response. When radio frequency radiation is shone onto the junction, the electrons in graphene heat up and dynamic resistance within the superconducting gap changes. The relation between absorbed power and temperature rise is used to characterize heat conductance and thermal noise equivalent power.   

Microwave transport and noise in graphene devices

We report on microwave transport and noise in graphene sheets, capacitors and transistors. We achieved a transit frequency of 80 GHz in graphene-on-sapphire transistors [1]. This is close to the state-of-the art for a 200nm gate length. In order to investigate electronic diffusion in graphene we have realized 10 GHz bandwidth experiments in metal-oxide-graphene capacitors. The crossover from capacitor to skin-effect limited cavity regimes provides an accurate and direct measurement of the diffusion constant D($\varepsilon )$. We find D to be energy independent, which points to a mass-disorder scenario [2]. Finally, we have measured the shot noise of CVD graphene in a broad range of bias up to 1V drain-source voltage. In our GHz-frequency measurements we observe a Fano factor exhibiting the three characteristic regimes of electron-impurity, electron-electron and electron-phonon interactions. \\[4pt] [1] E. Pallecchi et al, Appl. Phys. Lett. 99, 113502 (2011) \\[0pt] [2] E. Pallecchi et al, Phys. Rev. B 83, 125408 (2011)   

Anomalous noise characteristics in graphene p-n junctions

Graphene p-n junctions provide an interesting platform to study the Dirac nature of charge carriers, which gives rise to phenomena such as Klein tunneling and electron lensing. p-n junctions also play an important role in graphene nanodevices, but the ubiquitous low-frequency noise typically limits the device performance. It has been observed that the low-frequency noise for back-gated single layer and bilayer graphene decreases at the Dirac point, even though the resistance is maximal there. This decrease has been attributed to the effects of spatial charge inhomogeneity, and the noise in such devices decreases with decreasing temperature. We will present noise characteristics of dual-gated graphene p-n junction devices. At the Dirac point, the noise shows an ``M'' shape as a function of top gate voltage. Away from the Dirac point the shape changes depending on the back gate and top gate voltage. Unlike the low-frequency noise in graphene nanodevices, noise across the p-n junction decreases with increasing temperature. We also observed that the noise amplitude is larger in p-n-p or n-p-n devices than in p-p-p or n-n-n devices. We will discuss the mechanism that explains this anomalous noise behavior in graphene p-n junction.   

Incidence Angle-dependent Transport across a Single Graphene $p-n$ Junction Formed by Buried Split-gates

Due to electron chirality effects, carrier transport across Graphene $p-n$ junctions (GPNJ) is predicted to have strong angular dependence [1]. This work reports evidence of such effects in a single GPNJ for various geometries created by the use of buried split-gates (SG). Standard processes are used to fabricate 2-terminal Graphene devices aligned to buried Polysilicon SG at different angles to the junction. Sweeping the SG biases V1 and V2 allows mapping the doping-dependent device resistance (Rt). For doping levels (V1,V2), subtracting the average unipolar resistance Rt(V1,V1) from the bipolar resistance Rt(V1,V2) gives the average junction resistance Rj(V1,V2), subtracting out both contact and channel resistances. For bipolar doping, Rj shows a sharper peak for tilted channels than one that is normal to the junction, the peak being sharpest for 45\r{ }, the largest angle probed. This trend is observed for both exfoliated and CVD Graphene, especially for higher mobility and lower widths, consistent with theory. The ratio of the maximal Rj for 45\r{ } and 0\r{ } devices is about 2.5, significant for the modest Graphene mobilities of our devices. [1] V. Cheianov et al., \textbf{\textit{Science,}} \textbf{315}, 2007, pp 1252.   

Gate-Controlled P-I-N Junction Switching Device with Graphene Nanoribbon

The concept of a novel graphene P-I-N junction switching device with a nanoribbon is proposed, and its basic operation is demonstrated in an experiment. The concept aims to optimize the operation scheme for graphene transistors toward a superior on-off property. The device has two bulk graphene regions where the carrier type is electrostatically controlled by a top-gate, and these two regions are separated by a nanoribbon which works as insulator. As a result, the device forms a (P or N)-I-(P or N) junction. The off state is obtained by lifting the band of the bulk graphene of the source side and lowering that of the drain side, so that the device forms a P-I-N junction. In this configuration, the leakage current is reduced more effectively than the conventional single gate transistors due to a high barrier height and a long tunneling length in the nanoribbon. The on state is obtained by flipping the polarity of the bias of either top-gate to form a P-I-P or N-I-N junction. An experiment showed that the drain current was suppressed in the cases of P-I-N and N-I-P compared to P-I-P and N-I-N, and all of the behaviors were consistent with what was expected from the device operation model. This research is granted by JSPS through FIRST Program initiated by CSTP.   

Fabrication of suspended graphene heterojunctions for exploring the intrinsic transport of Dirac fermions

With linear energy dispersion and chirality, the quasiparticles in graphene differs from the conventional electrons in solid state systems in that the motions of the quasiparticles are governed by the Dirac Weyl equation. High quality of suspended graphene has made it possible to reach lower carrier densities and longer mean free paths and therefore has opened up the possibility of studying some of the unique, intrinsic properties of this Dirac electron system, which cannot otherwise be observed in conventional graphene devices on various substrates. To retain and exploit such properties of suspended graphene in heterojunction devices requires fabricating a contactless air top gate over the suspended graphene channel. Here we report on fabrication of such a device, which enable us to explore further, some interesting physics and transport of these Dirac fermions in graphene.   

Transport Properties of Gate Tunable Graphene-Based Tunnel Diodes

Due to its linear dispersion relation and unique physical properties, graphene has become a material of intense experimental and theoretical investigation. There has been rapid progress in the fabrication and understanding of graphene devices, particularly those based on the field effect transistor (FET) configuration. These three-terminal switches rely on a gate field to control electronic transport (diffusive or quasi-ballistic) in the graphene channel, where the field is perpendicular to the current flow. Here, a different type of three-terminal graphene device is demonstrated, one based on quantum tunneling. These devices build upon the convention two-terminal metal-insulator-metal (MIM) tunnel diode configuration by replacing one of the metal electrodes with graphene. Incorporation of a third (gate) electrode allows for modulation of the accessible density of states in the graphene electrode, thereby tuning the threshold voltage for tunneling in the diode. This tunable diode concept, where the gate field is parallel to the tunneling direction, is novel for a purely solid-state system. The device characteristics owing to the unique properties of graphene will be discussed, as will the underlying physics of device operation.   

Drain Current Saturation in Sub-$\mu $m Graphene Field Effect Transistors

Recently, graphene field-effect transistors (FET) with high cut-off frequencies (fT) were reported; however, the devices showed very weak drain current saturation, leading to an undesirably high output conductance. A crucial figure-of-merit for analog/RF transistors is the intrinsic gain (gm/gds). In this work, we show that by employing an embedded gate structure with an equivalent oxide thickness less than 2 nm, strong drain current saturation can be obtained for graphene FETs with short channels. The mechanism was not entirely due to velocity saturation, but rather the combination of a shift of the Dirac point in the voltage domain and a strong bias-dependent gate capacitance. The mechanisms are also verified with models.   

Self-aligned high transconductance CVD graphene transistor

Exceptional electronic properties of graphene make it a highly promising material for high-speed electronics. However, the design and practical realization of graphene transistors are still challenging, which limit the potential of graphene. In this work, we present a novel, practical, and highly scalable method for the fabrication of self-aligned graphene transistors. Large-area single-layer graphene films were grown on copper foil and were transferred onto 12 inch Si wafers. Furthermore, in order to achieve wafer-scale fabrication of graphene transistors with high yield, we developed a self-aligned fabrication approach by standard lithographical methods. The fabricated transistors with gate lengths in the range of 110 to 170 nm showed excellent performance with the peak current density of 1.3 mA/$\mu $m. The peak transconductance reaches 0.5 mS/$\mu $m, which is one of the best transconductance for CVD graphene transistor published up to date. Our novel fabrication method shows great potential toward practical implementation of graphene in high frequency devices and circuits.   

Graphene Enabled Vertical Field Effect Transistors

Vertical field effect transistors (VFETs) using a carbon nanotube source electrode have recently demonstrated state-of-the-art current densities at low operating voltages from comparatively low mobility organic semiconductors. Unlike in conventional thin film transistors, transconductance arises from a gate field modulation of the contact barrier at the organic semiconductor/nanotube interface (with the performance enhanced by nanotube Fermi level shifts allowed by their low density of electronic states). Graphene's low density of states near the Dirac point similarly makes it a good candidate source electrode in VFETs. We have now demonstrated such devices, facilitated by the use of a novel transfer technique that improves areal yields while avoiding both polymeric residue and the particulates that necessitate the use of thicker channel layers in nanotube VFETs. Critical to high performance is a facile method developed for perforating the graphene sheet with holes of a tunable size and density, allowing for a direct assessment of the role of self-screening effects in VFETs. These initial graphene enabled VFETs achieve on-current densities exceeding 250mA/cm$^{2}$ at drive voltage swings of less than 4V with on/off current ratios larger than 10$^{6}$.   

Transport/magnetotransport of high-performance graphene transistors on organic molecule-functionalized substrates

We present the transport and magnetotransport of high-quality graphene transistors on conventional SiO2/Si substrates by modification with organic molecule self-assembled monolayers (SAMs). Graphene devices on organic SAM-functionalized substrates exhibit high carrier mobility, low intrinsic doping, suppressed carrier scattering, and reduced thermal activation of resistivity at room temperature. Magnetotransport of graphene devices with pronounced quantum Hall effect and Shubnikov-de Haas oscillations also confirms the high quality of graphene on this ultrasmooth organic SAM-modified platform. The high-performance graphene transistors on the solution-processable SAM-functionalized SiO2/Si substrates are promising for the future development of large-area and low-cost fabrications of graphene-based nanoelectronics.   

Quantum transport simulation of graphene transistors

Owing to its unique electrical and thermal properties, graphene has attracted great interests as potential building blocks of next generation electronics, especially for RF applications. Due to lack of band gap, Klein tunneling plays an important role in sub-100nm graphene transistors. Inelastic phonon scattering introduced by intrinsic phonons of graphene and polarized substrate also affect device performance. We show that coupling between inelastic phonon scattering and Klein tunneling leads to different device physics of graphene transistors from common nanoscale transistors. The electron-phonon interaction and quantum transport in graphene transistors are modeled by the non-equilibrium green's function method within the self-consistent Born approximation. We evaluate the effect of inelastic process on both DC and RF performance of graphene transistors. We also briefly discuss the self-heating effects in graphene transistors introduced by inelastic phonon scattering.   

Pulse gating on graphene quantum dots

Graphene quantum devices have received increasing attention over the last years. Graphene quantum dots (QDs) are interesting systems for implementing spin qubits. Compared to well-established GaAs-based QDs, their smaller hyperfine and spin-orbit coupling promises more favorable spin coherence times. However, while the preparation, manipulation, and read-out of single spins have been demonstrated in GaAs, research on graphene QDs is still at an early stage. Although Coulomb blockade phenomena and excited state spectroscopy is now well established, experimental signatures allowing the identification of relaxation times have been hard to trace. Here we report on the current status of pulse gating experiments on graphene quantum devices and in particular we will present measurements of the charge relaxation rates in single-layer graphene QDs. The investigated devices consist of an island with a diameter of 120 nm, 4 lateral graphene gates and 2 charge detectors. From so-called diamond measurements we extract a charging energy of 11 meV and excited state level spacings on the order of 2-4 meV. The gates allow to individually tune the tunnelling-in and -out rates down to low MHz regime. Low-bias pulse gate measurements allow finally to extract relaxation rates on the order of 50 ns.   

Ultrafast conductivity measurements in CVD graphene

We study carrier dynamics in CVD graphene films on Al$_{2}$O$_{3 }$using time-resolved THz spectroscopy (TRTS). Excitation with a 50fs, 800nm pulse produces a conductivity change $\Delta \sigma $which we measure as a decrease in transmission of an ultrafast THz pulse. Ongoing work seeks to investigate TRTS in a magnetic field to directly probe scattering rates of photogenerated carriers. At present we report zero field measurements. We observe different recovery dynamics for low ($\Delta \sigma <<\sigma _0 )$ and high ($\Delta \sigma >\sigma _0 )$ pump powers. For pump fluence $\varphi <10^{12}\mbox{photons cm}^{-2}$ ($\Delta \sigma <<\sigma _0 )$ we find$\Delta \sigma \propto \varphi $ and observe a nearly exponential decay $\Delta \sigma \propto e^{-t/\tau }$with decay time $\tau \approx 2\mbox{ps}$. At higher powers ($\Delta \sigma >\sigma _0 ) \quad \Delta \sigma $ is sublinear in $\varphi $, and the decay rate decreases, with $\tau \approx 4\mbox{ps}$at $\varphi \approx 5\cdot 10^{13}\mbox{photons cm}^{-2}$. Graphene's unusual conductivity relation, $\sigma \propto \sqrt n _{,}$ predicts the observed behavior, since $\Delta \sigma \propto \sqrt {n_0 +n_{photo} } -\sqrt {n_0 } $ is approximately linear for $n_0 >>n_{photo} $, while $\Delta \sigma \propto \sqrt {n_{photo} } $for $n_{photo} >>n_0 $. Here $n_0 $ and $\sigma _0 $ are the equilibrium carrier density and conductivity in these p-type films. At high pump powers we also observe a rapid initial recovery on $\sim $500fs timescale which is not described by this simple model.   

Delay Analysis of Graphene Field Effect Transistors and T-Gate Self-Aligned GFETs

In this paper, we propose a new method for extracting the carrier transit delays in radio-frequency (RF) graphene field effect transistors (GFETs). This delay analysis not only gives deep physical insight into the carrier transport in the channel, but also provides valuable information that can guide the device engineers in optimizing the design of high performance RF GFETs. The contribution of this work is three-fold. First, GFETs are fabricated on sapphire substrate to reduce the parasitics from the GSG pads. This minimizes the error in measuring the S-parameter of the device and allows small-signal capacitances to be accurately extracted. Second, we present for the first time a detailed delay analysis of high frequency graphene transistors. Lastly, the simple and robust method proposed can accurately extract the intrinsic transit delay of the GFETs - the delay purely associated with the carrier transiting across the intrinsic gate region -- and allows a new method for direct experimental extraction of the average carrier velocity in the channel. Based on the analysis, we propose a self-aligned device structure to minimize the parasitic delays in GFETs. This GFET structure uses a T-shape gate as the mask to allow the source and drain metals to be aligned to the edge of the gate. A T-gate self-aligned GFET with gate head of 300 nm and foot 50 nm is fabricated and its DC and RF characteristics are reported.