APS March Meeting 2010
Volume 55, Number 2
Monday–Friday, March 15–19, 2010;
Portland, Oregon
Session Q33: Focus Session: Complex Oxide Thin Films -- Oxide/Semiconductor Interfaces and Defects
11:15 AM–2:15 PM,
Wednesday, March 17, 2010
Room: E143
Sponsoring
Units:
DMP GMAG
Chair: Susanne Stemmer, University of California, Santa Barbara
Abstract ID: BAPS.2010.MAR.Q33.1
Abstract: Q33.00001 : Interface chemistry between complex oxides and semiconductors: where chemistry and physics meet
11:15 AM–11:51 AM
Preview Abstract
Abstract
Author:
Chiara Marchiori
(IBM Research-Zurich)
Even though heavily based on semiconductors, microelectronics CMOS
technology would not exist without the integration of thin oxide
films which
enable the exploitation of the semiconductor properties. Indeed,
working
principle of the metal-oxide-semiconductor field-effect
transistor, the main
building block of such a technology, is the modulation of charges
at the
oxide/semiconductor interface. The quality of this interface is of
fundamental importance for device performance. For over four
decades,
SiO$_{2}$ was the gate dielectric of choice and device scaling meant
improving performance while lowering production costs. However,
as scaling
is approaching fundamental limits, direct tunneling across the
dielectric
becomes unacceptable. At this point, the integration of more
complex and
higher dielectric constant oxides - ``high-K dielectrics''- with
Si or even
more complex semiconductors (Ge, III-V) is the key enabler of
performance
gain.
I will review critical issues related to the oxide/semiconductor
interfaces,
starting with SiO$_{2}$/Si. Then, I will discuss how the level of
complexity
increases with the introduction of high-K dielectrics and other
semiconductors in the stack. Among the issues to be addressed to
fabricate
high-performance devices, I will discuss the role played by: 1)
interfacial
chemistry and thermodynamical stability, 2) band alignment and
surface band
bending, 3) presence of defects at the interface and in the oxide
bulk, 4)
evolution of the gate stack properties upon post-deposition
treatments. The
impact of these parameters on electrical performance of devices
will be
discussed in detail.
Finally, epitaxial oxide on Si will be explored as a promising
approach for
ultimate EOT scaling and the parameters governing the epitaxial
growth of
complex crystalline oxides on Si will be addressed. I will show
that the
development performed in this area might enable the integration
of epitaxial
oxides for monolithic integration, paving the way to technological
developments that go beyond the simple Moore's scaling law
To cite this abstract, use the following reference: http://meetings.aps.org/link/BAPS.2010.MAR.Q33.1