Session P3: Advances in Nanostructured Materials for Electronics

From nano to micro: hierarchical ordering at the nanoscale

The overall goal of controlling structural and electronic materials properties at nanometer length scales can be thought of as the intersection of two distinct but correlated challenges. The first is the synthesis/fabrication of individual nanoscale structures and the second is the arrangement of those structures into tailored nano- and micro-scale assemblies. Motivated by these twin challenges, the development of the superlattice nanowire pattern transfer (SNAP) technique has enabled the fabrication of highly ordered arrays of hundreds of nanowires (both metallic and semiconducting) at pitches down to 16 nm and aspect ratios up to 10$^{6}$. As a result of the hierarchical ordering of these assemblies (ranging from nanometer to micrometer length scales), it is possible to achieve electronic point-addressability within the arrays using traditional lithography. Further, iterative use of this technique to generate orthogonal nanowire arrays yields extremely dense crossbar circuits; with a bit density of $\sim $ 0.5 TBit/in$^{2}$ (10$^{11}$ Bits/cm$^{2})$ these structures approach crystallographic density. Both realized and potential applications of these structures ranging from ultra-dense electronic circuits to optical and electronic meta-materials will be discussed.   

Controlled formation of epitaxial III-V nanowires for device applications

For the realization of devices with dimensions on the 10 nm scale, there is today a great interest in the possible use of self-assembly as a tool. In this talk will be described the state-of-the-art in growth of epitaxially nucleated, vertically standing semiconductor nanowires made from III-V semiconductors, with high level of control of dimensions, position and structural properties. Such wires hold great promise for use in future electronics and photonics applications. Three key aspects will be specifically addressed, namely: \textbf{(1) The combination of top-down and bottom-up processes in lithographically aided formation of nanowires.} A concern from industry is that bottom up techniques should suffer from ``fundamental placement problem[s], i.e. there is no practical and reliable way to precisely align and position them.'' (Chau R., et al. Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications. (2005)). One way to resolve this issue is lithography where individual nanowire site control with high precision can be achieved. Electron beam lithography has the advantage of being a flexible high-resolution method, whereas nanoimprint lithography offers great opportunities for up-scaling and high-throughput processing. \textbf{(2) The successful growth of III-V nanowires on silicon, including designed heterostructures.} The special nanowire geometry with tens of nanometer radius and very small nanowire / substrate interface, enables monolithic integration of high-performance III-V materials on Silicon substrates. As an example, GaAsP heterostructure nanowires for photonic applications are discussed. Also the formation of InAs nanowires for high-speed and low-power-electronics directly on Si will be described. In the latter process, the use of foreign metal particles for wire growth is completely avoided, greatly reducing compatibility concerns between CMOS and nanowire technology. \textbf{(3) Nanowire devices}, such as field-effect transistors and light-emitting diodes will be discussed.   

Electron confinement and long-range interactions in 1-D atom chains

In nanostructures, when electrons are confined to reduced dimensions, the geometry of the confinement leads to the formation of quantized electronic states. In turn, these quantized states determine the energetic stability of a particular geometry. For systems that are self assembled, where thermodynamics and the cohesive energy can play a key role in the formation process, this interplay between the geometry of the confinement and the electronic states leads to the formation of nanostructures with ``magical sizes.'' Gold deposited on Si(553) leads to self-assembly of 1-D atomic chains, which are broken into finite segments by defects. Scanning tunneling spectroscopy measurements of the differential conductance along the chains revealed quantized states in isolated segments with differentiated states forming over the end atoms. These ``end states'' are the zero-dimensional analogs of the two-dimensional states that occur at a crystal surface[1]. Scanning tunneling microscopy was used to investigate the distribution of chain lengths and the correlation between defects separating the chains. The length distribution is not that for random defects, but exhibits oscillations that indicate changes in the cohesive energy as a function of chain length. We observe two separate components of the interaction and suggest a possible interpretation in terms of the electronic scattering vectors at the Fermi surface. The correlation function shows long-range correlations that extend beyond nearest-neighbor defects, indicating coupling between chains[2]. \begin{enumerate} \item J. N. Crain and D. T. Pierce, Science \textbf{307}, 703 (2005). \item J. N. Crain, M. D. Stiles, J. A. Stroscio, and D. T. Pierce, Phys. Rev. Lett. \textbf{96}, 156801 (2006). \end{enumerate}