2007 APS March Meeting
Volume 52, Number 1
Monday–Friday, March 5–9, 2007;
Denver, Colorado
Session P3: Advances in Nanostructured Materials for Electronics
11:15 AM–2:15 PM,
Wednesday, March 7, 2007
Colorado Convention Center
Room: Korbel 2A-3A
Sponsoring
Unit:
DCMP
Chair: John Wilkins, The Ohio State University
Abstract ID: BAPS.2007.MAR.P3.2
Abstract: P3.00002 : Controlled formation of epitaxial III-V nanowires for device applications
11:51 AM–12:27 PM
Preview Abstract
Abstract
Author:
Thomas Martensson
(Solid State Physics, Lund University)
For the realization of devices with dimensions on the 10 nm scale, there is
today a great interest in the possible use of self-assembly as a tool. In
this talk will be described the state-of-the-art in growth of epitaxially
nucleated, vertically standing semiconductor nanowires made from III-V
semiconductors, with high level of control of dimensions, position and
structural properties. Such wires hold great promise for use in future
electronics and photonics applications. Three key aspects will be
specifically addressed, namely:
\textbf{(1) The combination of top-down and bottom-up processes in
lithographically aided formation of nanowires.} A concern from industry is
that bottom up techniques should suffer from ``fundamental placement
problem[s], i.e. there is no practical and reliable way to precisely align
and position them.'' (Chau R., et al. Opportunities and challenges of III-V
nanoelectronics for future high-speed, low-power logic applications.
(2005)). One way to resolve this issue is lithography where individual
nanowire site control with high precision can be achieved. Electron beam
lithography has the advantage of being a flexible high-resolution method,
whereas nanoimprint lithography offers great opportunities for up-scaling
and high-throughput processing.
\textbf{(2) The successful growth of III-V nanowires on silicon, including
designed heterostructures.} The special nanowire geometry with tens of
nanometer radius and very small nanowire / substrate interface, enables
monolithic integration of high-performance III-V materials on Silicon
substrates. As an example, GaAsP heterostructure nanowires for photonic
applications are discussed. Also the formation of InAs nanowires for
high-speed and low-power-electronics directly on Si will be described. In
the latter process, the use of foreign metal particles for wire growth is
completely avoided, greatly reducing compatibility concerns between CMOS and
nanowire technology.
\textbf{(3) Nanowire devices}, such as field-effect transistors and
light-emitting diodes will be discussed.
To cite this abstract, use the following reference: http://meetings.aps.org/link/BAPS.2007.MAR.P3.2