Diagnosing hardware and gate errors in trapped ions using reduced Choi-matrix tomography*

Identifying and understanding hardware errors is crucial for assessing the performance of an experimental apparatus and enhancing the fidelity of the quantum circuits implemented within it. The initial step towards this goal involves the characterization of both the quantity and nature of error sources, specifically distinguishing between fluctuations and coherent errors from more intrinsic quantum errors. 

To accomplish this task, we introduce a benchmarking technique based on reduced Choi-matrix tomography [1, 2], the properties of which provide immediate and valulable insights into unknown quantum processes affecting the target unitary. Remarkably, this method eliminates the need for exhaustive knowledge of all noise sources affecting the system. 

We tested and validated the effectiveness of this technique on a single qubit gate implemented using a Calcium trapped ion. Furthermore, intentional noise injection served to confirm the method's reliability for error detection and identification.

This approach can be easily extended to cover the two-qubit gate scenario, and seamlessly integrated into the regular calibration and maintenance procedures for the experimental hardware. 

[1] B. H. Madhusudhana. Benchmarking multi-qubit gates – I: Metrological aspects, 2023, arXiv: 2210.04330.

[2] B. H. Madhusudhana. Benchmarking multi-qubit gates – II: Computational aspects, 2023, arXiv: 2301.07109.