Track reconstruction for the ATLAS Phase-II High-Level Trigger using Graph Neural Networks on FPGAs with detector segmentation and regional processing*

The High-Luminosity LHC (HL-LHC) will provide an order of magnitude increase in integrated luminosity and enhance the discovery reach for new phenomena. The increased pile-up foreseen during the HL-LHC necessitates major upgrades to the ATLAS detector and trigger. The Phase-II trigger will consist of two levels, a hardware-based Level-0 trigger and an Event Filter (EF) with tracking capabilities. Within the Trigger and Data Acquisition group, a heterogeneous computing farm consisting of CPUs and potentially GPUs and/or FPGAs is under study, together with the use of modern machine learning algorithms such as Graph Neural Networks (GNNs).

A key design consideration for the Phase-II EF system is the ability to process an entire event for track candidates within a single FPGA. Current studies are exploring GNNs for track reconstruction. The large graphs used in full detector events present a challenge for processing within a single FPGA. We explore a possible solution by processing regions of the detector through the GNN sequentially to reduce the required resources. We employ a GNN-based EF tracking pipeline: graph construction, edge classification using an interaction network, and track reconstruction. We present an approach that uses sequential processing of graphs constructed in regions of the detector aimed to minimize FPGA resources utilization and maximize throughput while retaining high track reconstruction efficiency and low fake rates required for the ATLAS Phase-II EF tracking system.