Bulletin of the American Physical Society
70th Annual Gaseous Electronics Conference
Volume 62, Number 10
Monday–Friday, November 6–10, 2017; Pittsburgh, Pennsylvania
Session ET3: Plasma Etching for Semiconductor Processing |
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Chair: SangHeon Song, Lam Research Room: Oakmont Junior Ballroom |
Tuesday, November 7, 2017 10:00AM - 10:30AM |
ET3.00001: Etching for New Devices Invited Speaker: Keizo Kinoshita Information network and services are now one of the most important social infrastructure. They have been growing by progression of LSI devices. An important characteristic of the LSI device is function extendibility by integrating new materials and new device concepts. Plasma processes are key fabrication technologies of the LSI devices, and have been confronted to meet various requirements. Two topics will be presented here. First topic is Silicon Photonics (SiPh) which is a newly-proposed device for data communications. It has come to reality by applying the CMOS process technology on optical devices. However, there are points to be modified. One is nanometer-order control of line-edge-roughness at a very wide Si waveguide patterning. An ArF immersion lithography and a gate etching technique for 55 nm technology node and after were applied to fabricate a 440-nm-wide Si waveguide [1]. Low optical propagation loss of 0.5 dB/cm was achieved. The other is a light source integration on the SiPh device. A MEMS deep etching process was applied to fabricate a pedestal to mount a laser diode chip [2]. Second topic is magnetic material integration to realize MRAM. We need to deposit a multilayered transition metal/oxide stack film by PVD, and fabricate magnetic dot array with a few tens of nanometers in diameter without deteriorating magnetic properties. However, chemical modifications of the materials are indispensable to proceed reactive ion etching. To overcome this issue, a recovery process by reductive chemistry was proposed as an after treatment of the methanol plasma etching, and obtained comparable performances with an Ar ion etched non-damage sample [3]. [1] S.-H. Jeong, et al., Opt. Express, 21, 30163 (2013). [2] K. Kinoshita, et al., AVS 63rd Symp., PS-ThP18, (2016). [3] K. Kinoshita, et al., Jpn. J. Appl. Phys., 51, 08HA01 (2012). [Preview Abstract] |
Tuesday, November 7, 2017 10:30AM - 10:45AM |
ET3.00002: Cryogenic etching: A solution for damage-free narrow trench etching Quanzhi Zhang, Stefan Tinck, Annemie Bogaerts Porous materials are commonly used in microelectronics, as they can meet the demand for continuously shrinking electronic feature dimensions. However, they are facing severe challenges in plasma etching, due to plasma induced damage. A hybrid Monte Carlo-fluid model is employed to investigate cryogenic C$_{\mathrm{4}}$F$_{\mathrm{8}}$ plasma etching of porous materials. It is shown that the plasma induced damage gradually decreases with lowering the substrate temperature, which allows that C$_{\mathrm{4}}$F$_{\mathrm{8}}$ condenses inside the pores. Negligible plasma induced damage can be achieved around $-$110 \textdegree C. However, the etching rate is reduced due to the pore filling with C$_{\mathrm{4}}$F$_{\mathrm{8}}$. The simulation results of both etching rate and plasma induced damage as a function of wafer temperature are validated by experimental results, performed at imec. [Preview Abstract] |
Tuesday, November 7, 2017 10:45AM - 11:00AM |
ET3.00003: Machine Learning of Micro/macro Cavity Data for Etching Recipe Optimization Hyakka Nakada, Masaru Kurihara, Masayoshi Ishikawa, Tatehito Usui, Naoyuki Kofuji, Takeshi Ohmori Semiconductor manufacturing processing has been complexed and the process development period has been prolonged with the progress of device structure from 2D to 3D. The long development period causes the increase of the device cost. In plasma etching process, a set of the control parameters of etcher is called as recipe. Rapid optimization of the recipe to obtain a target profile has been required to reduce the development period. A recipe exploration method based on machine learning of feature data related to etching profile is developed to accelerate the recipe optimization. Micro/macro cavity method [1] is used to extract the feature data. An approximately region to obtain a vertical etching profile as a target can be determined in the feature data space because the feature data show the characteristics of ion assist etching and radical etching. The correlation between the feature data and recipes is learned by a machine learning model. The recipes for the vertical profile are predicted by the learning model. Three recipes to etch the vertical profile were found from only seven times of Si trench etching using the recipes predicted by the learning of 60 sets of the feature data. [1] K. Watanabe and H. Komiyama, J. Electrochem. Soc., vol. 137 (1990). [Preview Abstract] |
Tuesday, November 7, 2017 11:00AM - 11:30AM |
ET3.00004: Atomic Layer Etch: A Concurrent Plasma Modeling and Process Approach Invited Speaker: Mingmei Wang Atomic layer etching (ALE) has been investigated over decades and is getting more attention recently than ever due to its potential capability of solving grand challenges in advanced node plasma etch. As feature size shrank to nanometer scale, etch issues such as ARDE, loading, etch stop, top clogging etc. turned to be more severe than in more relaxed patterning schemes. However, ALE, as a promising solution to all problems in traditional etch methods, has its own challenges. Questions that are frequently asked regarding self-limiting process, productivity, hardware capability, etc. have to be considered during an ALE process development. To precisely control ALE processes, fundamental understanding of the surface interactions during etch is required. In this talk, we will discuss concurrent engineering approaches including both modeling and experiment to understand and develop ALE etching processes that meet grand challenge requirements. The core of the approach is an integrated chamber scale HPEM (Hybrid Plasma Equipment Model)-feature scale MCFPM (Monte Carlo Feature Profile Model) model [1]. The concurrent engineering approach comprises stages of development and prediction capability tests using both blanket wafer and patterned stack data and finally process parameter optimization. By using this approach, we are able to provide insights on how to resolve grand challenges in plasma etch with a minimum of engineering resources. The presentation will survey both experimental and computational results representing a few case studies in SAC quasi-ALE, Si ALE, Si3N4 ALE, etc. Furthermore, insights into the relationship between chamber function and critical surface interactions will be discussed. [1] M.Wang and M.Kushner, J. Appl. Phys~107, 2010. [Preview Abstract] |
Tuesday, November 7, 2017 11:30AM - 11:45AM |
ET3.00005: Selective Etching by Tailored RF Ion Energy Control Using Frequency/Phase Locked RF Power Delivery Yusuke Yoshida, David Coumou, Scott White, Steven Shannon, Sergey Voronin, Alok Ranjan The control of the ion energy distribution function (IEDF) for surface interaction remains a vexing challenge for semiconductor process engineers. Exploiting frequency and phase locked RF power delivery for sheath voltage manipulation presents a unique method for ion energy control. By regulating the skew of the ion energy distribution, we achieve improved fidelity of etch rate control. Experimental sputtering and etch yields for oxide and nitride films are obtained from measured IEDFs and etch rate data. By tailoring the ion energy peak location and the overall shape of the IEDF, we preferentially ``delegate'' more ions to the optimal ion energy group while minimizing the surface material impingement of other energy bands. This ability to customize IEDFs yields a process enhancement for precise material removal compared to conventional techniques, offering a great potential for etch applications at atomic scale (say ALE) processes. [Preview Abstract] |
Tuesday, November 7, 2017 11:45AM - 12:00PM |
ET3.00006: VUV Broad-Band absorption spectroscopy in downstream plasma soft-etch reactor Robert Soriano Casero, Laurent Vallier, Gilles Cunge, Nader Sadeghi The patterning of nanometer scale features in complex stacks of ultrathin layers is a challenging plasma process.Plasma induced damage is a serious issue when dealing with ultrathin layers and adverse topography.As a result, there is a regain of interest for remote(downstream)etching reactors,in which the wafer is etched in the absence of ion bombardment by radicals only.However,downstream systems have been poorly characterized and are typically using complex plasma chemistry at relatively high pressure(≥1Torr). In this work we used VUV Broad Band absorption spectroscopy, described in[1],with a VUV CCD camera to detect closed shell molecules(NF3,NH3,HF..)in downstream NF3/H2 and NF3/NH3 plasmas,which are used to etch selectively Si,Si3N4 and SiO2. We focus on the production and loss mechanisms of HF, which seems to be the main etching agent,and discuss the impact of the plasma operating conditions on the HF density.Further,we show that due to the high sensitivity of the VUVAS,it is possible to monitor in real time the radical densities(NF3, NH3, HF),which is useful to understand their production and loss kinetics and also to provide an endpoint technique adapted to these reactors.in which the currently used optical emission for this purpose is not present. [1] G.Cunge et al,2011 [Preview Abstract] |
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