Bulletin of the American Physical Society
APS April Meeting 2016
Volume 61, Number 6
Saturday–Tuesday, April 16–19, 2016; Salt Lake City, Utah
Session H7: Porting Particle Accelerator Codes on Emerging Computer ArchitecturesInvited
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Sponsoring Units: DPB DCOMP Chair: Jean-Luc Vay, Lawrence Berkeley National Laboratory Room: 150G |
Sunday, April 17, 2016 8:30AM - 9:06AM |
H7.00001: PIC codes for plasma accelerators on emerging computer architectures (GPUS, Multicore/Manycore CPUS) Invited Speaker: Henri VINCENTI The advent of exascale computers will enable 3D simulations of a new laser-plasma interaction regimes that were previously out of reach of current Petasale computers. However, the paradigm used to write current PIC codes will have to change in order to fully exploit the potentialities of these new computing architectures. Indeed, achieving Exascale computing facilities in the next decade will be a great challenge in terms of energy consumption and will imply hardware developments directly impacting our way of implementing PIC codes.$\backslash $pard $\backslash $pardAs data movement (from die to network) is by far the most energy consuming part of an algorithm future computers will tend to increase memory locality at the hardware level and reduce energy consumption related to data movement by using more and more cores on each compute nodes ("fat nodes") that will have a reduced clock speed to allow for efficient cooling. To compensate for frequency decrease, CPU machine vendors are making use of long SIMD instruction registers that are able to process multiple data with one arithmetic operator in one clock cycle. SIMD register length is expected to double every four years. GPU's also have a reduced clock speed per core and can process Multiple Instructions on Multiple Datas (MIMD).$\backslash $pard $\backslash $pardAt the software level Particle-In-Cell (PIC) codes will thus have to achieve both good memory locality and vectorization (for Multicore/Manycore CPU) to fully take advantage of these upcoming architectures. In this talk, we present the portable solutions we implemented in our high performance skeleton PIC code PICSAR to both achieve good memory locality and cache reuse as well as good vectorization on SIMD architectures. We also present the portable solutions used to parallelize the Pseudo-sepctral quasi-cylindrical code FBPIC on GPUs using the Numba python compiler. [Preview Abstract] |
Sunday, April 17, 2016 9:06AM - 9:42AM |
H7.00002: A portable approach for PIC on emerging architectures. Invited Speaker: Viktor Decyk A portable approach for designing Particle-in-Cell (PIC) algorithms on emerging exascale computers, is based on the recognition that 3 distinct programming paradigms are needed. They are: low level vector (SIMD) processing, middle level shared memory parallel programing, and high level distributed memory programming. In addition, there is a memory hierarchy associated with each level. Such algorithms can be initially developed using vectorizing compilers, OpenMP, and MPI. This is the approach recommended by Intel for the Phi processor. These algorithms can then be translated and possibly specialized to other programming models and languages, as needed. For example, the vector processing and shared memory programming might be done with CUDA instead of vectorizing compilers and OpenMP, but generally the algorithm itself is not greatly changed. The UCLA PICKSC web site at \underline {http://www.idre.ucla.edu}/ contains example open source skeleton codes (mini-apps) illustrating each of these three programming models, individually and in combination. Fortran2003 now supports abstract data types, and design patterns [1] can be used to support a variety of implementations within the same code base. Fortran2003 also supports interoperability with C so that implementations in C languages are also easy to use. Finally, main codes can be translated into dynamic environments such as Python, while still taking advantage of high performing compiled languages. Parallel languages are still evolving with interesting developments in co-Array Fortran, UPC, and OpenACC, among others, and these can also be supported within the same software architecture. [1] E. Gamma, R. Helm, R. Johnson, and J. Vlissides, `Design Patterns: Elements of Reusable Object-Oriented Software,'' [Addison-Wesley, 1995]. [Preview Abstract] |
Sunday, April 17, 2016 9:42AM - 10:18AM |
H7.00003: Astrophysics PIC codes on manycore systems Invited Speaker: Salman Habib |
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