3D Integration for Extensible Quantum Processors*

As superconducting qubit performance continues to evolve, we must also address the interconnect challenge for superconducting quantum processors (SQPs). Multi-level wiring and heterogeneous integration developed for classical integrated circuits can be optimized for SQPs. 3D integration technologies require optimization for superconducting quantum systems since many integration technologies contain normal metals and lossy dielectrics which can compromise the performance of superconducting qubits. Integration technologies include air-bridges for crossing signals [1]; flip-chip integration with indium bump bonds and silicon hard-stop spacers to couple multiple chips [2,3]; superconducting through silicon vias to route signals through chips [4] and enable novel circuit elements [5]; multilevel planarized wiring to support complex routing schemes [6]; and multi-tier stacks which can enable complex control and readout of superconducting quantum arrays [4,7,8].  I will discuss challenges of implementing and vetting 3D heterogeneous technologies to enable extensible superconducting qubit processors. 

 

[1] D. Rosenberg et al., IEEE microwave (2020) 

[2] D. Rosenberg et al., npj QI (2017) 

[3] B. M. Niedzielski et al., IEEE IEDM (2019) 

[4] Yost*, Schwartz*, Mallek*, et al., npj QI (2020) 

[5] T. Hazard, et.al. APL (2023) 

[6] Tolpygo et al., IEEE Appl. Supercond. (2016) 

[7] Karamlou et al., arXiv:2306.02571v3 (2023) 

[8] C. Barrett et al., Phys. Rev. Appl. (2023)