Session W46: Silicon Qubits IV - Characterization and Modeling

Defining Specifications for Si/SiGe Qubit Devices Using Multiphysics Modeling Methods

The design of large-scale spin qubit arrays and their control infrastructure require expertise from various domains of semiconductor technology. In an industrial manufacturing environment, the design of qubit arrays will hence strongly benefit from defining clear specifications for various design parameters. Here, we employ a suite of Multiphysics simulation techniques to model Si/SiGe qubit devices and correlate them to experimental results to define parameter specifications for the qubits and for the devices hosting them. These include qubit related parameters such as qubit frequency, Rabi frequency, exchange coupling & spin coherence times – along with device parameters such as device potential uniformity, magnetic field gradients, isotopic purification, crosstalk, charge-noise and defect density. These specifications will be used to design the next generation spin qubit arrays at Intel.   

Si/SiGe spin qubit with full 300mm process

300mm process line has demonstrated its effeciency in producing  spin qubits in silicon, confirming the idea that this platform is one of the most promising candidates for large scale quantum computers. In addition to scalability, the high reproducibility of 300mm processes allows a deterministic study of qubit metrics dependence on process parameters, essential for improving qubit quality. At IMEC, we built a strategy to efficiently optimize all the process parameters to produce better qubits.

Here we demonstrate the effectiveness of this strategy by reporting the latest results obtained on Si/SiGe quantum devices: valley-splitting around 100 µeV, charge noise values of 1 µeV/√Hz, double dot tunnel coupling tunability over 3 order of magnitude up to 100GHz, spin relaxation times above 1s and coherence time T2* and T2 respectively of 1 µs and 45 µs for natural silicon.   

Technology computer-aided design simulations of spin qubits in gated double quantum dots

The design and engineering of classical silicon-based microelectronics often relies on a mature set of computational tools. Among these tools are technology computer-aided design (TCAD) software which are used to predict device performance and trends before fabrication. As we move toward using silicon for quantum technologies in the form of, e.g., spin qubits, it seems plausible that we will need to adopt best practices employed for classical semiconductor systems. However, because of the fundamental differences in operating principles between classical and quantum hardware, specialized quantum TCAD tools must be developed for quantum systems. In this work, we use the spin-qubit device modeling software package QTCAD to perform TCAD simulations of double-dot devices. In particular, we compute charge-stability diagrams, tunneling rates, and exchange energies in specific electron and hole silicon double-dot devices (e.g., FD-SOI devices) and predict how these properties can be modified by changing experimental configurations, starting only from device layouts and design rules. We identify schemes (e.g., based on the lever-arm and Hubbard approximations) which present sufficient accuracy while keeping computation times compatible with the rapid simulation requirements of the semiconductor industry.   

Radio frequency reflectometry measurements on industrial CMOS Double Quantum Dot using superconducting spiral inductor

Silicon spin qubits, with their long coherence time and compatibility with industrial CMOS technology, hold great promise for large-scale quantum computing. As the number of spin qubits per chip continues growing, building industrial compatible devices is required for the necessary level of scalability and reproducibility to reach fault-tolerant quantum computing. In addition, a method for spin readout that minimizes the footprint is essential to achieve a large-scale quantum processor. In this context we present a reflectometry measurements of a spin compatible double quantum dot fully fabricated in a 300 mm integrated process at the IMEC manufacturing facility.

Our reflectometry measurement uses a Nb superconducting spiral inductor, improving the quality factor of the tank circuit. Through an analysis of the reflected signal's amplitude and phase, we can discern crucial electronic properties of the quantum dots, including electronic temperature and tunneling rate, providing invaluable insights into their behavior and applications.

 

This research was undertaken thanks in part to funding from the Canada First Research Excellence Fund. We acknowledge the support of the Natural Sciences and Engineering Research Council of Canada (NSERC).   

Tunnel and capacitive coupling optimization in FDSOI spin-qubit devices

The possibility to form well defined and long lived spin qubit in silicon as well as their compatibility with industrial CMOS technology have made them an attractive choice for building a large scale quantum computer. Within dense arrays of quantum dots (QDs), precise fine-tuning and accurate determination of operating conditions will be imperative for each individual spin qubit.

Here we present the ongoing development to improve the sturdiness of individual spin qubits within a scalable design. We aim to suppress the diagonal coupling in pseudo-2D array structures compared with the longitudinal and transverse couplings for a proper device operability. To this end, we introduced new QDs array designs and developed dedicated gate/active module accordingly. Higher yield was achieved through process optimization of the two-level intertwined gates structures.  Finally, low temperature characterization of the proposed structures show wide tunability of the tunnel coupling.   

Tuning and operation of quantum dots using FPGA tools tailored for spin qubits

Main challenges in the development of a spin qubit quantum processor include tuning of large arrays of quantum dots to compensate for dot-to-dot variability and fast operation of gates which control the quantum dots for the implementation of error-correcting protocols.

Here, we offloaded parts of the tuning procedure from the lab computer to the instrument itself using the on-board field-programmable gate arrays (FPGAs) of Keysight’s Quantum Engineering Toolkit (QET).

The waveforms for a stability diagram measurement are generated on-the-fly without communication with the lab computer during the measurement. This allows video-mode measurements of small voltage regions for real time fine-tuning[ED1] . Furthermore, virtual gates can also be used by sending only the coefficient matrix since the compensation calculations are done in less than 100 ns in the FPGAs. With this approach, the tuning of a CMOS quantum dot has been done and compared to a traditional tuning procedure that does not use FPGAs. Moving the control logic of an experiment closer to the instruments and sample [ED2] allow for faster feedback and potentially faster measurements. It also offers a new tool to implement more scalable tuning and control for spin qubits.   

Gate-based spin readout in planar Si-MOS quantum dots using an off-chip microwave resonator.

Planar Si-MOS technology provides a promising platform to build scalable two-dimensional arrays with nearest neighbor connectivity needed to implement, efficiently, the surface code [1]. Reflectometry techniques can perform spin read-out through the gate and are therefore a promising approach to read out dense two-dimensional qubit arrays without compromising the qubit connectivity. However, in planar technologies, efforts to achieve high-fidelity gate-based read-out have been hindered by multiple factors, such as lower gate lever arms and parasitic two-dimensional electron gases in accumulation mode devices. In this work, we interface the quantum device fabricated on a 300mm wafer with a newly developed high-impedance off-chip resonator at 1.32 GHz. With our approach, we demonstrate dispersive detection of an inter-dot charge transition with a state-of-the-art signal-to-noise ratio of 1 in 100 us in planar Si-MOS [2] and perform singlet-triplet spin readout via Pauli spin blockade.

[1] Li et al. 2018, “A crossbar network for silicon quantum dot qubits”, Science Advances.

[2] West et al. 2019, “Gate-based single-shot readout of spins in silicon”, Nature Nanotechnology.   

Charge-noise spectroscopy using exchange oscillations in Si/SiGe spin qubits

Electron spins in silicon quantum dots are a promising qubit platform due to their long coherence times, small footprint, and compatibility with industrial fabrication. Recent advances with isotopically purified silicon and heterostructure quality have enabled single-qubit and two-qubit fidelities beyond the threshold for fault-tolerant operation, limited by charge-noise in the host semiconductor. We measure the charge-noise spectrum in a Si/SiGe singlet-triplet qubit on Intel’s latest testchip [1], over nearly 11 decades of frequency using exchange oscillations biased in the detuning-sensitive regime. Dynamically decoupling low-frequency noise with up to 128 π-pulses [2] enables the design of filter functions to probe charge-noise at tens of MHz, revealing a 1/f spectrum over the entire frequency range of our measurements. The charge-noise spectrum provides key insights for evaluating heterostructure quality, fabrication process flows, and developing noise mitigation strategies, including dynamically corrected gates for suppressed noise sensitivity and higher single and two-qubit fidelities.

1. Neyens, S., Zietz, O., et al. arXiv:2307.04812

2. Connors, E.J., et al. Nat. Commun. 13, 940 (2022)   

Reconfigurable quadruple quantum dot linear array with tunable couplings and dispersive sensing

We discuss measurement results on a device that we show can demonstrate spin-based manipulation and readout in a multi-gate CMOS device. An array of four dot gates in series control the charge occupancy of their respective underlying quantum dots, while five independently tuneable exchange gates regulate their inter-dot coupling. Such a structure can form the basis of various qubit device configurations, whether that be a 4 quantum dot device or a 2 or 3 quantum dot device along with a corresponding sensing quantum dot.

 

The readout is performed using both DC measurement of the CMOS nanowire, as well as gate-based radio-frequency reflectometry readout. Two resonators, with superconducting spiral inductor and capacitor pairs designed in-house capable of delivering high quality factors, are connected to the dot gates to allow the reflectometry readout; the other two dot gates connect to microwave sources allowing pulses, suitable for real-time operation of the quantum dot.   

Fast cryogenic probing of quantum dot spin qubit devices

Fast feedback from cryogenic electrical characterization measurements is key for the successful development of scalable quantum computing technology. At room temperature, high-throughput device testing is accomplished with a probe-based solution, where electrical probes are repeatedly positioned onto devices for acquiring statistical data. In this work, we present a probe station that can be operated from room temperature down to 1.4 K [de Kruijf et al., Rev. Sci. Instrum. 94, 054707 (2023)]. It is designed for 2x2 cm² chips, that are moved with respect to a multi-contact probe card using closed-loop piezo-based positioners. This prober is compact enough to fit inside a standard cryogenic magnet system and is compatible with both direct-current and radio-frequency signals, thereby making it a versatile tool perfectly suited for gathering statistical data on qubits. A large variety of electronic devices can be tested. We showcase the performance of the prober by characterizing silicon fin field-effect transistors as a host for quantum dot spin qubits [Camenzind and Geyer et al., Nat. Electron. 5, 178 (2022)]. Such a tool can massively accelerate the design-fabrication-measurement cycle and provide important feedback for process optimization toward building scalable quantum circuits.

 

Supported by the NCCR SPIN, Swiss NSF, and the Georg H. Endress Foundation.   

Spin Qubits with Integrated millikelvin CMOS Control

A key virtue of spin qubits is their tiny submicron footprint, enabling billions of qubits to fit on a single silicon wafer. With each qubit requiring a handful of gate electrodes for control, however, a formidable challenge arises in the management of this extreme interconnect density. Monolithic integration of qubits with CMOS-based control circuits can potentially address this challenge, although the impact of heat and crosstalk on the qubits is likely to pose a significant risk to this approach. An alternate architecture¹ leverages heterogeneous ‘chiplet’ style packaging in which the control circuits and qubits are proximal, but positioned on separate dies and wired-up using dense, lithographically defined interconnects at milli-kelvin temperatures. Here, we report the realization of a cryo-CMOS control architecture (based on 28 nm FDSOI) and benchmark its performance using silicon MOS-style electron spin qubits². The fidelity of both single- and two-qubit gate operations acts to probe the impact of heat and noise arising from the cryo-CMOS control circuits. These results suggest that heterogeneous integration is a viable means of scaling-up the control interface of spin-based quantum processors.  

1. Pauka, S.J., Das, K., Kalra, R. et al. A cryogenic CMOS chip for generating control signals for multiple qubits. Nat Electron 4, 64–70 (2021). https://doi.org/10.1038/s41928-020-00528-y

2. Veldhorst, M., Yang, C., Hwang, J. et al. A two-qubit logic gate in silicon. Nature 526, 410–414 (2015). https://doi.org/10.1038/nature15263   

Characterization of Cryo-CMOS heating and noise properties using Silicon spin qubits

Cryo-CMOS has previously been demonstrated as a promising control interface for large-scale spin qubit quantum computation. However, its substantial heat dissipation has limited its integration to the 4K stage of a dilution fridge. In this talk, we employ an approach developed earlier in our group [1], utilizing Cryo-CMOS at an ultra-low temperature of 20 mK. Leveraging spin qubits as probing tools, we conduct a comprehensive examination of the Cryo-CMOS chip's thermal and noise properties and their concurrent impact on spin qubits across a wide parameter space. Our findings provide valuable insights for enhancing cryo-CMOS technology, particularly in the context of its heterogeneous integration with silicon spin qubits, advancing the prospects of quantum computing architectures.

[1] Pauka, S.J. et al.  Nat Electron 4, 64–70 (2021)   

Characterization of Multiple Qubit Encodings in Industrially-Manufactured Silicon Quantum Dots

Silicon-based spin qubits in lithographically defined quantum dots (QDs) are a promising platform for quantum computing due to their ability to use established silicon growth and processing technologies. These devices are operated using a variety of different qubit encodings that may have distinct advantages and disadvantages. Here, we explore two encodings that utilize baseband pulsing techniques to provide localized control of single qubits. The singlet-triplet encoding requires two electrons and two QDs with universal single-qubit control accomplished by evolution of the state in the presence of a magnetic field gradient between electron spins and the exchange interaction. In contrast, the exchange-only encoding provides universal single-qubit control through only the modulation of the exchange interaction, at the cost of requiring three electrons and three QDs and introducing additional leakage states. We present experimental realizations of both encodings in a single isotopically enriched, industrially-manufactured Si/SiGe quantum device. We characterize and compare operation of the different encodings to weigh their advantages and disadvantages for quantum computation.   

Oral: Advances in Spin Qubit Devices: Interconnect and Magnet Optimization for Scalability

Recent developments in control of spin qubits have shown exciting results [1,2]. In order to successfully scale quantum chips to larger numbers of high-fidelity qubits, improvement in the quality of the material is necessary. In this talk, we present some of our recent work on metals, magnetic material, and dielectric material analysis used in the fabrication of our spin qubit devices. Such analyses are critical to get a better understanding on how to improve performance of our devices to increase scalability. First, we describe the multi-layered test structures added alongside the spin qubit devices in order to evaluate how material properties change throughout the fabrication process [3]. We find that selected fabrication steps lead to increase in the resistivity of the palladium interconnects. Then, we discuss the optimization of the magnetic films used to create the micromagnets that are used for qubit driving and addressability. Finally, with metal-insulator-metal devices, we evaluate the quality of the dielectric material and show what impact the lithographic process (e.g., optical vs. e-beam) has on its reliability.