Session S46: Spin Qubit Arrays

A 2x2 Quantum Processor in 28Si/SiGe

Some of the largest semiconductor-based quantum processors are constrained to a linear arrangement of qubits. Executing an algorithm in such one-dimensional arrays demands an excessive overhead and requires higher fidelities to meet error correction thresholds. Thus, it is crucial to expand these linear arrays in the second dimension and increase the connectivity of each qubit. While in other platforms such as GaAs or Ge/SiGe 2D arrays were successfully implemented, such a demonstration has not yet been realized in Si/SiGe.

We present control over a 4-qubit device in a square 2x2 configuration. The device is based on a ²⁸Si/SiGe heterostructure, with each quantum dot tuned to the single electron regime. Utilizing an on-chip micro magnet we selectively drive single-qubit rotations using resonant microwave bursts. Dedicated barrier gates between neighboring quantum dots allow us to implement two-qubit gates between qubits while staying at the noise-resilient symmetry point. Finally, we will present the latest experimental results on crosstalk effects and small-scale algorithms realized in this device.   

Improving measurement techniques and infrastructure for the milli-kelvin characterization of quantum dot devices

Electron spin qubits hosted in quantum dots are a promising platform for quantum computing as they are dense, coherent, and can be integrated with advanced semiconductor manufacturing. A key challenge is achieving sufficient uniformity in these devices to scale to larger arrays as the properties of quantum dots can be influenced by many aspects of the solid-state environment such as disorder or the atomistic details of interfaces. Important to this task is to find fast and reliable methods to measure and build statistics across many quantum dots and devices, allowing the comparison of different integration processes and materials different integration processes and materials. Here we detail the measurement infrastructure and techniques used to measure disorder and extract valley and orbital splittings, charge noise, exchange tunability, and coherence over multiple devices and wafers fabricated at Intel [1]. 

[1]  S. Neyens, O. Zietz et al.  “Probing single electrons across 300 mm spin qubit wafers”.   

Scalability of of semiconductor quantum dot architectures: shared control, qubit addressability, and connectivity

The efficient control of a large number of qubits is one of the most challenging aspects for practical quantum computing. Current approaches in solid-state quantum technology are based on brute-force methods, where each and every qubit requires at least one unique control line, an approach that will become unsustainable when scaling to the required millions of qubits [1].

In this talk, I will present our progress in this direction and detail our ambitions to advance the state-of-the-art of semiconductor qubits toward fault-tolerant quantum computing. In our path, we adopt concepts from random access architectures in classical electronics and introduce the shared control of semiconductor quantum dots to efficiently operate a two-dimensional crossbar array in planar germanium [2].  We demonstrate the tune-up and the identification of each of the 16 quantum dots of the array in the few-hole regime and establish a method for the selective control of the quantum dot interdot coupling.

Finally, we consider a minimal 2x2 qubit array and investigate both experimentally and theoretically the bichromatic electric dipole spin resonance technique as a method for spatially selective qubit rotations in larger crossbar arrays [3]. We demonstrate coherent bichromatic rotations with Rabi frequencies exceeding 1 MHz, and observe resonance anticrossings originating from the ac Stark shift. I will conclude by presenting our efforts in tuning and controlling a 10-quantum dot qubit system as the basis for the next generation of experiments based on low-power, low magnetic field and high-fidelity quantum gates [4].

1. Franke et al., Microprocess. Microsyst. (2018)

2. Borsoi et al., Nature Nano. 1-7 (2023)

3. John, Borsoi, Gyorgy et al., arXiv:2308.01720 (2023)

4. Wang et al., in preparation (2023)   

Readout of spin qubit arrays made by advanced semiconductor manufacturing

Silicon-based quantum processors can leverage advanced semiconductor processing, offering a promising path to the large qubit count required for reaching computational advantage. High-fidelity quantum state readout is a core element of a quantum processor and requires carefully designed cryogenic readout circuits and has been demonstrated using both cryo-amplifier circuits and radio-frequency reflectometry techniques. In this talk, we discuss our current approach for readout of our 12-quantum dot array Tunnel Falls chip with onboard HBT-based cryo-amplifiers enabling high-fidelity Pauli-spin-blockade readout. We then detail progress towards scaling and improving readout to larger arrays and benchmarking different readout approaches.   

Adiabatic Electron Spin Resonance Inversion in an FDSOI Quantum Dot Array

Toward realization of a practical quantum computer, scalability of qubits is ​essential and still quite challenging[1]. In order to overcome this technical challenge, we developed a two-dimensional quantum dot array using FDSOI (Fully-Depleted-Silicon-on-Insulator), which has large scalability by sophisticated commercial semiconductor technology [2]. For spin-based quantum computer, qubit manipulation technique that combine electron spin resonance and single-shot readout is required. Here, we integrate the quantum dot array together with a charge sensor by self-aligned double-gate patterning process. By utilizing an improved self-alignment process, it is possible to reduce the distance between the gates applied to the qubit array and charge sensor, making it possible to achieve both improving the controllability of the qubit and readout sensitivity in the qubit array. In addition, we introduce adiabatic rapid passage to invert spin state using chirped microwave. As a result, we could demonstrate clear electron spin resonance signals in our proposed silicon quantum dot array.

References

[1] N. Lee et al., Jpn. J. Appl. Phys. 61, SC1040 (2022).

[2] M. Shafiei et al., Phys. Rev. Lett. 110, 107601 (2013)   

Fabrication and characterization of multi-rail Si/SiGe exchange-only spin qubits in the SLEDGE architecture

Si/SiGe exchange-only spin qubits encoded in a decoherence-free subsystem (DFS) are a compelling platform for quantum computing because of their compatibility with advanced fabrication techniques and their exclusive use of baseband pulses for control.  Using the Single-Layer Etch-Defined Gate-Electrode (SLEDGE) architecture [1], which implements a CMOS-like separation between active front-end gates and electrical routing layers, we recently demonstrated high-fidelity two-qubit DFS-encoded gates [2] in a single-rail device.  Scaling to multi-rail geometries, where qubits are connected to more than two neighbors, is an essential step towards quantum fault tolerance because it improves robustness and connectivity. We report on the fabrication of a two-rail, six-dot device with three distinct back-end routing layers. We also discuss the electrostatic tune-up, the initial parametric characterization, and the single-qubit randomized benchmarking performance of this device. 

[1] W. Ha et al., Nano Lett., 22, 1443 (2021)

[2] A. Weinstein et al., Nature 615, 817 (2023)   

High-connectivity SiGe quantum dot devices using the SLEDGE architecture

Si-SiGe quantum dots are a promising platform for scalable quantum computing. In order to increase the connectivity of spin qubits, it will be necessary to make a transition from conventional linear quantum dot arrays [1, 2] towards more complex geometries. One such geometry of interest is the triangular quantum dot array, where three quantum dots may be mutually exchange-coupled to one another. By eliminating interstitial field gates, a triangular dot array only requires a single metal layer of back-end routing when using the SLEDGE device architecture [2]. Here we show full configuration interaction simulations of such a triangular device, providing confidence that the device can be tuned into a state where all three dots reach single electron occupancy and provide adequate control of the exchange coupling [3,4].  We also discuss the realization of these structures and preliminary measurements.

[1] D. M. Zajac et al., Phys. Rev. Applied 6, 054013 (2016)

[2] S. Ha et al., Nano Lett. 22, 1443 (2022)

[3] A. S. Pan et al., Quantum Sci. Technol. 5, 034005 (2020)

[4] C. R. Anderson et al., AIP Advances 12, 065123 (2022)   

High-fidelity dispersive spin readout in a scalable unit cell of silicon quantum dots

Planar MOS multi-gate technology is one of the leading approaches to silicon-based quantum computing. For readout of spin qubits, dispersive sensing offers the potential of scalable unit cells by avoiding the need for multiple charge reservoirs. So far, demonstrations of planar MOS quantum dots have been restricted to architectures where sensors are co-linear with the qubit array, limiting scalability. Achieving readout fidelity at the level of control operations has also remained challenging. In this work, we address both limitations: we demonstrate single-shot spin readout with fidelity above 99.9% measured in 400 us in a planar MOS quantum dot array fabricated using a 300mm wafer process. We use a single electron box (SEB) to measure the two-electron spin state of a double quantum dot using Pauli spin blockade. The sensor and qubit dots are placed in parallel channels of a bilinear array of quantum dots, forming a compact unit cell. The high fidelity is achieved thanks to the tunability of the structure that allows (i) optimization of the tunnel rate of the SEB for enhanced signal and (ii) tuning of the coupling between the double quantum dots using a J-gate, leading to an enhancement of the singlet-triplet relaxation time from 4 us to 0.5 s. Overall, this work demonstrates sensing in a compact unit cell with state-of-the art fidelity, providing a path to scalable high-connectivity bilinear qubit arrays.   

Quantum LDPC Error Correcting Codes for use on 1D Quantum Dot Arrays

Building upon recent advancements that have demonstrated the shuttling of qubits through a quantum dot array with high fidelity, we conceive of a complete error correction architecture, consisting merely of two parallel quantum dot arrays. One of those two arrays is allowed to "shift" left and right, with different positions allowing for different connectivity between the qubits within the quantum computer. We devise a suite of heuristic methods for compiling any ECC circuit to run with an approximately minimal number of "shifts" of the array. Through simulation we find that fault tolerance can be achieved on several contemporary quantum error correcting codes using only modestly-optimistic noise parameters and the compilation techniques we propose here.   

Dephasing mechanisms and fidelity of entangled spin qubits preparation under joint continuous measurement via longitudinal couplings to a superconducting resonator

We consider the preparation dynamics of spin qubits entanglement via joint continuous measurement with longitudinal couplings to a superconducting resonator (see [1]). Enhancement of the measurement rate via the dynamical longitudinal coupling allows to effectively overcome the typical dephasing mechanisms, such as charge dephasing and qubit relaxation. Another dephasing mechanism originates from the unitary back action arising in a homodyne measurement. We show how it can be cancelled for a system of N qubits in an appropriate limit when the resonator dynamics is much faster than the qubits rates. We study these mechanisms on the realistic example of a charge-spin qubit with magnetic field gradient, and discuss possible experimental signatures of the spin-qubit entanglement.

 

 [1] R. Ruskov and C. Tahan, Phys. Rev. B 99, 245306 (2019); arXiv: 1704.05876   

Design of an Intel Quantum Control Processor for Quantum Computers

Quantum Computers are growing in scale, which means that the control requirements are also growing. Qubit control electronics are commonly used and discussed, but in this talk we introduce the Quantum Control Processor (QCP), which is responsible for orchestrating the control electronics using inspiration from classical CPU design. The QCP interprets Quantum Instruction Set Architecture (QISA) binary instructions (an extension of standard CPU instructions) into low-level control signals that are distributed to analog signal generators. The QCP will allow scalable control of a quantum processor by enabling: addressing large numbers of qubits, automatic gate recalibration, error correction & logical qubit operation and distributed processing for hybrid quantum algorithms. In this talk, we discuss the key design considerations and elements of the QCP and the QISA.