Optimizing Josephson junction area and the fabrication process of superconducting quantum processors to reduce two-level system defects

Josephson junction (JJ) qubits offer a scalable technological path for realizing superconducting quantum processors potentially capable of Quantum Advantage. Cryogenic performance of qubits is impacted by design and process choices, as well as material selection and the interaction between materials at interfaces, and interaction with the environment. The impact of two-level system defects on qubit performance is a concern even in flux-tunable qubits. We report on our efforts to improve qubit performance by reducing the JJ area through fabrication process changes and compare qubit performance (TLS, coherence) across JJ sizes and barrier transparency. We achieve greater than 50% reduction in the impact of two-level system defects on qubits by reducing junction areas by a similar fraction, while keeping the overall inductance target of the JJs the same.