APS March Meeting 2024
Monday–Friday, March 4–8, 2024;
Minneapolis & Virtual
Session Q20: Frontiers in Growth for Applications II
3:00 PM–6:00 PM,
Wednesday, March 6, 2024
Room: M101ABC
Sponsoring
Unit:
DCMP
Chair: Nicholas Pike, Air Force Research Lab
Abstract: Q20.00001 : Controllable fabrication of wafer-scale MoS2 thin films and the flexible integrated circuit
3:00 PM–3:12 PM
Abstract
Presenter:
Dongxia Shi
(Chinese Academy of Sciences,Institute of Physics)
Author:
Dongxia Shi
(Chinese Academy of Sciences,Institute of Physics)
As a new two-dimensional (2D) semiconductor material, monolayer molybdenum disulfide (MoS2) has wide application potential in advanced electronics technologies beyond silicon due to its atomic thickness and no dangling bond surface. In addition to the monolayer, multilayers MoS2 have narrower band gaps but improved carrier mobilities and current capacities. To realize the application of MoS2 in integrated circuits, the most important thing is the low power consumption and high performance of the device, which depends heavily on the quality of the material and the processing technology of the device. Controllable preparation of wafer-scale high-quality MoS2 films is the material basis for device applications, and higher requirements are also put forward for device manufacturing technology of ultra-thin two-dimensional materials. So far, high-quality monolayer MoS2 wafers have been available and various demonstrations from individual transistors to integrated circuits have also been shown. However, achieving high-quality multi-layer MoS2 wafers remains a challenge. Firstly, based on the self-developed oxygen-assisted chemical vapor deposition method, we have grown high-quality, uniform 4-inch wafer-scale single-layer and multi-layer MoS2 films via the layer-by-layer epitaxy process on sapphire substrates. The epitaxy leads to well-defined stacking orders between adjacent epitaxial layers and offers a delicate control of layer numbers up to six. Further, we developed a metal-buried gate combined with ultra-thin gate dielectric layer deposition process. By preferential processing of the gate electrode and deposited ultra-thin high-κ dielectric film on the gate electrode, we successfully reduce the high dielectric constant HfO2 gate dielectric layer thickness to 5 nm and the corresponding equivalent oxide thickness (EOT) to 1 nm. The FET devices on the prepared hard substrate have low power consumption, high current density and ultra-low leakage current with negligible hysteresis. At the same time, by optimizing the metal deposition process, the contact between the metal electrode and MoS2 can be made without any damage avoiding Fermi level pinning, and the contact resistance can be reduced to Rc< 600Ω ·μm. Then this process was applied to the manufacture of flexible devices. Due to the improvement of gate voltage regulation efficiency, the full-function large-scale flexible integrated circuit of MoS2 integrated on the flexible substrate can be operated at a voltage lower than 1V. Our research work provides a technical reserve for the development of 2D semiconductor-based integrated circuits in flexible portable, wearable, and implantable electronics.