Empirical overhead of the adapted surface code on defective qubit arrays

The realization of fault-tolerant quantum computers using solid-state hardware will require us to adapt our quantum error correction procedure to account for fabrication variation and defects that will invariably arise. If unaddressed, these errors inhibit us from scaling our system such that quantum information can be processed with sufficiently small failure rates.

We simulate the surface code adapted to defective qubit arrays to find metrics that characterize how defects affect fidelity. We then use our simulations to determine the impact of defects on the resource overhead of realizing a fault-tolerant quantum computer, on a chiplet-based modular architecture. Our QEC simulation adapts the syndrome readout circuit for the surface code to account for an arbitrary distribution of defects. Our simulations show that surface code adapted to defective arrays still has an exponential suppression of logical failure where error rates of non-defective physical qubits are ~0.1% for a circuit-based noise model. We use our numerical results to establish post-selection criteria for assembling a device with defective chiplets. We then evaluate the resource overhead due to defects. We find that an optimal choice of chiplet size, based on the defect rate and target performance, is essential to limiting any additional error correction overhead due to defects. We also determine cutoff fidelity values that help identify whether a qubit should be disabled or kept as part of the error correction code.