Bulletin of the American Physical Society
APS March Meeting 2024
Monday–Friday, March 4–8, 2024; Minneapolis & Virtual
Session MM03: V: DMP General Physics I
5:30 AM–7:30 AM,
Thursday, March 7, 2024
Room: Virtual Room 03
Sponsoring
Unit:
DMP
Chair: Sanjeev Kumar, University College London; Dan-Adrian German, Indiana University Bloomington
Abstract: MM03.00006 : Demonstrating High Performance, Ultra-Low Power with High Photoresponsivity of Van der Waals Transistors for Back-End-of-Line Machine Vision Applications
6:30 AM–6:42 AM
Presenter:
Moh R Amer
(King Abdulaziz City for Science and Technology)
Author:
Moh R Amer
(King Abdulaziz City for Science and Technology)
Collaborations:
Sarah Alsaggaf, Olaiyan Alolaiyan, Shahad Albawardi
In this context, we investigate new lithography strategy identified under modified van der Waals (vdW) deposition method. We showcase a relatively novel 2D-FETs called van-der-Waals-Field-Effect-Transistors (vdW-FETs) based on 2D materials. This fabrication strategy empowers us to create high-performance devices, evident by a substantial current on-off ratio (Ion/Ioff), a high turn-on current density (Ion), and a reduced Fermi Level Pinning (FLP). We apply this method to show a gate-tunable near-ideal diode utilizing a MoS2/WSe2 heterojunction, which exhibits an ideality factor of approximately 1.65 and a high current rectification.
Furthermore, we demonstrate an exceptionally sensitive, scalable, and ultra-low power photodetector using MoS2/WSe2 vdW-FETs, designed for Back-End-of-Line (BEOL) integration. Our photodetector sets a new standard for gate-tunable photoresponsivity for white light detection, achieving ultra-low power consumption. This unique gate tunable photodetector based on MoS2/WSe2 vdW-FETs paves the way for ultra-sensitive, rapid, and efficient in-sensor machine vision. Our approach underscores the immense potential of modified vdW deposition lithography for Back-End-of-Line CMOS+2D.
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