Scaling Hardware-Based Quantum Error Correction via a Multi-Context Approach*

The theory of quantum error correction is well understood, though its practical implementation remains challenging. This is due to the low-latency requirements for the classical computations that are required to carry out the quantum error correction. Recent advancements have shown that it is possible to meet these requirements for surface codes using algorithms implemented in FPGA hardware [1]. While it has been shown that the execution time of the algorithm scales favorably with increasing physical qubit numbers, the hardware ressource consumption grow to the third power, limiting the maximum number of qubits that can be used.

Here we present a way to reduce hardware ressource consumption by using a multi-context approach, trading hardware ressources for execution time. By saving some state of the error decoder in memory, we avoid time consuming network connections, which would otherwise be required to overcome the limitations of a single FPGA chip. The technique we are presenting is developed with our own approach to the Union-Find algorithm in mind [2], but is sufficiently general to be used with all algorithms which work on decoder graphs with limited connectivity.

[1] N. Liyanage et al., Scalable quntum error correction for surface codes using FPGA (IEEE FCCM, Marina Del Rey, CA, USA 2023)

[2] M. Heer el al., Novel union-find-based decoders for scalable quantum error correction on systolic arrays (IEEE IPDPSW, St. Petersburg, FL, USA 2023)