Progress Toward Coherent Photon Arithmetic on a Superconducting Bosonic Mode*

The rates of most primitive quantum logical operations on n-level systems are state-dependent. This makes arithmetic operations on n-level systems challenging as they require a-priori knowledge of the system state. A prior proposal [1] has shown the theoretical implementation of coherent single-photon subtraction (SPS) from a bosonic mode to an auxiliary qubit by combining two simultaneous drives. One drive irreversibly swaps an excitation from a bosonic mode to an auxiliary bit using dissipation engineering. The other drive makes the first operation coherent by irreversibly exciting the auxiliary bit to its second excited state. In this work, we make progress toward experimentally realizing the proposal on a superconducting processor. We support these experimental results with numerical simulations including up to fourth-order interactions.

[1] Christopher McNally, Max Hays, and William D. Oliver “Single-Photon Subtraction in Circuit QED,” (2023), APS March Meeting