Transferable Learning on Analog Neural Network Hardware*

Analog neural network (NN) accelerators promise tremendous energy and time savings but process-induced random static fabrication errors in each individual analog chip pose a challenging obstacle to widespread analog NN deployment. Neural network models produced by standard training methods for programmable photonic interferometer circuits, a leading analog NN platform, yield poor performance on real chips that have static component fabrication errors. Moreover, existing hardware error-aware training/mitigation techniques either require individual retraining of every analog NN chip (which is impractical in an edge setting with millions of devices to be retrained worldwide), place stringent demands on component quality, or introduce hardware overhead. We solve all three problems by introducing error-aware training techniques that need to be run only once to produce robust neural network models that match the performance of ideal hardware and can be transferred exactly, without any performance loss or additional retraining, to any number of arbitrary highly faulty photonic NNs at the edge with hardware errors up to five times larger than present-day fabrication tolerances.