Session B46: Scaling Up Silicon Qubits - Characterization and Fab

Toward high-throughput characterization of random spin baths in semiconductors

Spin-defects in semiconductors, such as nitrogen-vacancy centers in diamond or divacancies in silicon carbide, are promising candidates for qubits, due to their optical addressability and relatively long coherence times. In most semiconductors, the hyperfine interaction of the central defect spin with isotopic nuclear spins is the main source of decoherence. Currently there are no automatic and efficient techniques for high-throughput characterization of local random nuclear spin baths in materials containing spin-defects, since direct experimental characterization is too time-consuming and labor-intensive for many samples. Although we can efficiently simulate dynamical decoupling experiments for a given configuration of nuclear spins, the inverse problem of recovering the hyperfine interactions from short dynamical decoupling experiments is ill-posed [1]. Using simulated data, however, we can augment short dynamical decoupling experiments to interpret the reliability and accuracy of hyperfine couplings extracted from these experiments. We developed a set of tools that can be used to validate the mathematical and physical bounds on proposed sets of hyperfine couplings obtained from data-driven, machine-learned, or advanced sampling methods. These tools can be used to guide experimental design for dynamical decoupling protocols and pave the way for high-throughput characterization of defects in semiconductors.

[1] M. Onizhuk & G. Galli. Adv. Theory. Simul. 2100254 (2021).   

On the variability of fin-shaped silicon spin qubit with multi-gate: effect of gate work function variation

A multi-gate quantum dot structure is expected as a Si spin qubit in integrated qubit arrays. In multi-gate devices, potential valleys and barriers are electrostatically formed near the Si surface by biases applied to the gates, and precise control of the potential profile is essential for qubit operation with high fidelity. Here, work function variation (WFV) of the gates, which is one of factors to cause variability in conventional MOSFETs, could be an inhibiting factor also to aiming at higher qubit fidelity. Therefore, in this study, we investigated the influence of WFV based on 3D device simulation (HyENEXSS^TM) at 300K, subjecting to a fin-shaped single quantum dot device. The device consists of a p-type body and n+-type source/drain, with one plunger gate (PG), two barrier gates (BG), and two accumulation gates (AG). We particularly focused on the threshold voltage (Vth) in a characteristic of source-to-drain current controlled by PG bias (Ids-Vpg) as a standard of the bias, following to the well-established manner in conventional MOSFET. We found that Vth of Ids-Vpg is shifted due to the WFV of not only PG but also BG. It means that WFV of surrounding gates, i.e., gates not targeted for operation, also influences. On the other hand, it is clarified that the level of conduction band edge just beneath PG does not vary when Vpg is set to be Vth, although the Vth value itself is shifted due to the WFM of BG. This also suggests that the concept of Vth is available to examine the performance variability of multi-gate Si qubits.   

Progress Towards an Integrated Flip-Chip Quantum Dot Platform for the Rapid Characterization of Semiconductor Qubit Materials

Recent demonstrations of high fidelity multiqubit operations in semiconductor based gated lateral quantum dot (QD) qubits are often limited by fundamental properties of the materials used, and further understanding and optimization of the qubit materials is necessary. However, rapid characterization techniques for both bulk and nano-scale materials properties for QD qubits are lacking, particularly for research level groups where the initial investment of fabricating semiconductor qubits is overwhelming. We are developing a flip-chip QD platform that contains all the necessary circuit elements for the gating and readout of lateral QD qubits, which can be confined in an arbitrary material of interest without the investment of material specific fabrication techniques. A robust vacuum gap between the gates and the QD material of interest is engineered by indium bump bonding techniques with precisely etched hard stop posts and mesas. We achieve a separation of less than 100 nm with a deviation of 22 nm, which is robust to cooling to cryogenic temperatures. The proposed qubit readout scheme is dispersive gate readout via a superconducting resonator that is fabricated on the gate-side flip chip. We will present an integrated design that combines all the gating and readout elements necessary to characterize QD qubits and their host materials.   

High volume characterization techniques for industry manufactured Si/SiGe spin qubit devices

As spin qubit devices advance in size and complexity, improvements in component yield and process variation will be increasingly necessary to obtain high performance devices. Towards this end, high volume cryogenic measurement will be critical both to optimize fabrication processes as well as to identify the highest performing devices to package in a quantum computing stack. In this talk we review measurement techniques from the Intel Quantum Hardware group to characterize industry manufactured spin qubit devices with a 300 mm cryogenic wafer prober at 1.6 K. We present the latest high-volume data on Intel's spin qubit process and demonstrate how advances in spin qubit component yield combined with a low disorder Si/SiGe host material lead to a high success rate for spin qubit applications.   

Stable Al-based SETs for Si-based Spin Qubit Readout

Using a novel plasma oxidation technique, we have overcome the instability problem in metal-based single electron transistors (SETs) and are fabricating stable AlOx-based SETs with the goal of improved output current and ease of measurement. While metal-based SETs were extensively studied more than 20 years ago, they were not feasible as qubit charge sensors due to instability issues. By minimizing defects in the tunnel junction through plasma oxidation, we have achieved a remarkable reduction in charge offset drift (∆Q0 = 0.13 e ± 0.01 e over 7 days), a significant improvement compared to previous literature. Therefore, we are seeking to produce aluminum-based SETs using plasma oxidation that can be coupled to Si-based quantum dots for precise charge-sensing purposes. The main deficiency in these SETs now is the limited output current at ~4 pA level, which we are aiming to increase to ~100 pA. To achieve this, we are varying the AlOx tunnel junction oxidation time from our nominal 7 s, expecting reduced time will decrease the resistance. We expect to report the results from the SET devices with varying oxidation times as well as show their long-term stability in this talk.   

Local laser-induced solid phase recrystallization in Si/SiGe: forming Ohmic contacts with reduced heat load for spin qubit applications

Silicon/silicon-germanium (Si/SiGe) heterostructures have emerged as a prominant host material for electron spin qubits, with small-scale Si/SiGe devices achieving operation fidelities surpassing the error-correction threshold. Scaling this approach further, it is foreseeable that the reliance of qubit parameters on their atomistic environment will lead to inter-device fluctuations, which will significantly impede approaches like spin shuttling [1]. Hence, methods for minimizing temperature-activated diffusion and post-growth strain relaxation become crucial, as increasingly complex layer structures are being developed to improve parameters like valley splitting [2]. However, the current state of the art relies on globally raising the device temperature to electrically activate the ion-implanted Ohmic contacts, which compromises the carefully engineered layer stack in the active qubit region.

To address this challenge, we have devised a laser-based local annealing process for the recrystallization of ion-implanted contacts. This approach substantially reduces the thermal load on the active device area. Utilizing this process, we have successfully fabricated Hall bar structures, demonstrating electron mobility and contact resistance values that are as good as, or even superior to, those of a globally annealed reference sample.

[1] T. Struck, M. Volmer, L. Visser, T. Offermann, R. Xue, J.-S. Tu, S. Trellenkamp, Ł. Cywiński, H. Bluhm, and L. R. Schreiber, Spin-EPR-Pair Separation by Conveyor-Mode Single Electron Shuttling in Si/SiGe, http://arxiv.org/abs/2307.04897 (2023).

[2] M. P. Losert, M. A. Eriksson, R. Joynt, R. Rahman, G. Scappucci, S. N. Coppersmith, and M. Friesen, Practical Strategies for Enhancing the Valley Splitting in Si/SiGe Quantum Wells, http://arxiv.org/abs/2303.02499 (2023).   

Oral: Cryogenic current and amplifier development for spin-to-charge readout

Advanced silicon-based quantum computing depends on the development of both analog and digital classical circuits operating in close proximity to qubits, requiring these circuits to function in cryogenic environments. Ideally, these circuits will be in the same silicon as the qubits, providing the switching, amplification, and thresholding for performing qubit manipulation and projective readout. However, the even simple component properties (resistance, capacitance, etc.) change dramatically between room temperature and cryogenic temperatures. Therefore, developing cryogenic helper circuits depends on developing new component and circuit models for cryogenic temperatures. In this talk, I will first present results from a series of measurements starting with simple, easily sourced components like capacitors, resistors, and transistors at cryogenic temperatures. I will then show results from simple current mirror and differential voltage amplifier circuits constructed from these components and implemented at cryogenic temperatures. Finally, I will show characterization measurements and ad hoc models from custom, foundry made transistors and discuss progress toward developing larger circuit models for monolithic implementation.    

Characterizing Valley Splitting in Si/SiGe Quantum Devices Using a Scanning Gate Microscope Tip-Induced Quantum Dot

            A solid understanding of the materials properties that affect the splitting between the two low-lying valley states in Si/SiGe heterostructures will be increasingly important as the number of qubits is increased [1]. Scanning gate microscopy (SGM) has been proposed as a method to measure the spatial variation of the valley energies as the tip-induced dot is moved around in the plane of the Si quantum well [2]. Utilizing domain decomposition techniques, an electrostatic model of the SGM tip bias and the 3D overlapping gate structure can be combined with an approximate solution to the 3D Schrödinger-Poisson equation [3]. With these simulation tools, we show that a tip-induced quantum dot formed near source and drain electrodes can be adiabatically moved to a region far from the gate electrodes. By spatially translating the tip-induced dot across a defect in the Si/SiGe interface, changes in valley energy splitting can be detected.

 

[1] Burkard et al., Phys. Rev. B 94, 195305 (2016)

[2] Shim et al., Appl. Phys. Lett. 114, 152105 (2019)

[3] Anderson et al., J. Comput. Phys. 228, 4745 (2009)   

Counteracting decoherence induced by spin-valley coupling in single-qubit manipulation zones via quantum optimal control

Quantum bus architectures based on electron spin shuttling in a Si/SiGe heterostructure are promising candidates for scalable quantum computing. Electrically controlled single qubit gates are achieved with a carefully placed micro-magnet that provides a synthetic spin-orbit coupling in the designated manipulation zones [Künne et al. arXiv:2306.16348 (2023)]. The presence of spin-valley hotspots at the vicinity of the micro-magnet can cause spin decoherence, limiting the capability to achieve fault tolerant gates. Using quantum optimal control techniques, we obtain new electron trajectories leading to significant improvements to the gate fidelity. The influence of valley splitting and the distance from spin-valley hotspots are also investigated, based on statistical sampling of prototypical device configurations. For increasing values of spin-valley coupling, 99.12% of the samples converged below the required fault tolerant gate fidelity threshold, where all of the under-performing samples are due to a high value of spin-valley coupling.   

RF Diode Thermometry – Pushing the limits of cryogenic temperature sensing

Addressing and operating the large number of qubits needed for fault-tolerant quantum computing requires the integration of classical circuitry close to or on the same chip as qubits operating at cryogenic temperatures. These classical circuits dissipate power which may affect qubit operation. Experimental tools to probe these static and dynamic effects are therefore of interest to the field and will lead to a better understanding of the recent temperature-dependence observed in semiconductor spin-qubit systems. Previously it has been shown that diode thermometry is the most sensitive cryogenic thermometry technique native to CMOS devices. In this work, we further increase the sensitivity of diode thermometry by using radiofrequency reflectometry (RF) techniques and demonstrate state-of-the-art cryogenic temperature sensing capabilities, maintaining sensitivity down to 20mK. The technique allows us to conduct pulsed heating experiments with a resolution of <1µs commensurate with that achieved in semiconductor qubit architectures. The ability to probe at high frequency provides insight into the dynamic temperature behavior of the chip as a result of both localized (on-chip) and global (PCB) level heating. This technique will allow future experimental studies of quantum thermodynamics in nanoelectronic systems as well as increase our understanding of dynamic power dissipation in cryoelectronic and quantum circuits.   

A Millikelvin CMOS Demultiplexing Chip for Scalable Qubit Addressing

Large-scale silicon qubit control requires accurate biasing and gate pulsing for several terminals of a multi-qubit device. Continuous pulsing enables sequential quantum operations, while simultaneous pulsing on multiple terminals enables real-time cross-talk compensation. Conventional qubit addressing provides DC bias and gate pulsing using commercial instruments at 300 K, while recent innovation in cryo-CMOS control can move select signal generation to 4 K. In both approaches however, cabling, power and noise constraints becomes a bottleneck for controlling large qubit/SET arrays. To address the cabling bottleneck, certain aspects of the control system should be moved closer to the qubits at the mK stage.

In this work, we present a mK cryo-CMOS demultiplexer chip that uses a single DC bias generator and a single pulse generator as inputs, to demultiplex voltages for up to 64 qubit device terminals and provide both DC bias, and simultaneous and continuous high-speed gate pulses. To further alleviate cabling bottlenecks, a 4 K cryo-CMOS controller provides the control signals and gate pulsing voltage to the mK demultiplexer. Integrated with a foundry manufactured qubit chip on the same PCB, mK cryogenic measurements show multi-terminal characterization of a qubit device.