Bulletin of the American Physical Society
APS March Meeting 2023
Volume 68, Number 3
Las Vegas, Nevada (March 5-10)
Virtual (March 20-22); Time Zone: Pacific Time
Session Q34: Semiconductor Materials for Beyond CMOS Electronics |
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Sponsoring Units: FIAP Chair: Yong Zhong, Stanford University Room: Room 226/227 |
Wednesday, March 8, 2023 3:00PM - 3:12PM Author not Attending |
Q34.00001: Nonequilibrium dynamics of perovskite wide-bandgap oxides under high-density carrier injection Hui-Yuan Chen Wide bandgap oxides (WBGOs) have widely emerged in modern photonics such as transparent conducting oxides in photovoltaics or gate oxides in power electronics [1~4]. Perovskite WBGOs provide the additional advantage of seamless integration with extended functionalities such as ferroelectricity and superconductivity in other perovskites, enabling future compact multifunctional devices [5,6]. Barium stannate (BaSnO3, BSO) recently rose as the most studied perovskite WBGO for its wide doping range and outstanding electron mobility of 320 cm2/(Vs) among WBGOs [7]. The low electron effective mass at conduction band minimum, mainly composed of the strong antibonding Sn 5s-orbital, explained its superior mobility. However, transient electronic structural dynamics of BSO immediately after carrier injection into the conduction band is not easily accessed and thus has not been fully understood. The early fate of injected carriers is deterministic for the ultimate formation of photocurrent in photovoltaics as well as reliability in power electronics. In this study, we mimic transient carrier injection into BSO via ultrafast above-gap photoexcitation and revealed its sub-picosecond carrier dynamics with UV transient absorption (TA) spectroscopy across the bandgap. A fast hot-carrier cooling lifetime of 1ps due to electron-phonon scattering along with clear exciton bleach and excitonic enhancement resulting from photo-excited free carriers are unveiled. |
Wednesday, March 8, 2023 3:12PM - 3:24PM |
Q34.00002: Interfacial Engineering on Metal/2D Material Interfaces Chih-I Wu, I-Chi Ni Atomically thin two-dimensional (2D) semiconductors have great potential for realizing high-performance electronic devices. However, the performance of 2D material-based devices is frequently limited by the interfacial issues between and contact metal and 2D materials. In this presentation, we are going to present the latest results on the interfacial engineering of metal/2D materials in both transistors and interconnects. In the first part of the presentation, we report a high performance 2D-channel transistor with drive current compatible with Si devices. Through ultra-low contact technology between semimetal and semiconducting monolayer transition metal dichalcogenides (TMDs). We achieve a record high on-state current density (ION) of 1135 μA/μm on monolayer MoS2. The thermal stability of the 2D-channel transistor are improved with choice of various semimetals. The second part of the presentation, we will report the progress on applying the 2D materials in backend process. Graphene is deposited on Cu as capping layer at low temperature (< 400 C) and improve the electromigration effects. We also use CVD process to successfully form graphene layers around the Co line as liners at backend compatible temperature, which we expect could also improve the reliability of the Co interconnects. |
Wednesday, March 8, 2023 3:24PM - 3:36PM |
Q34.00003: Understanding of the Interaction between Electrical and Thermal Properties on Bifunctional Memristors and Reprogrammable Memory Justin B Stouffer, Ying-Chen Chen, Yao-Feng Chang, Yifu Huang In this work, an engineered sub-µm-scale via-type one-time programmable (OTP) memory and self-rectified resistive switching memory (ReRAM or Memristor) are demonstrated. The current development has achieved co-existing memory functionality (OTP and ReRAM) with mitigating scaling limitation (fuse voltage trending with via size scaling), low fabrication complexity (via-fuse vs. gate-dielectric anti-fuse), and matches with the current CMOS technology. In addition, an engineered electrode and stacking structures have been proposed to realize ultra-low programming voltage (~1.9V) in via-type OTP featuring by metal-insulator-metal advanced BEOL process with ruthenium materials. The impact of via-size, programming window, stacked structures, and integration capability has been extensively studied using COMSOL Multiphysics Simulation tool to understand the interactions between the electrical and thermal properties on simple metal-insulator-metal device structures, where it exhibits dual functionality of ReRAM and OTP. The result shows that the switching gap contains the hottest temperature throughout the device, specifically in the low-k dielectric layer. Our results provide a pathfinding and an understanding of the mechanism dealing with high density, integration capability, low programing voltage, multi-functionality between programmable read-only memory (PROM) and resistive switching memory co-existing in future embedded applications. |
Wednesday, March 8, 2023 3:36PM - 3:48PM |
Q34.00004: Contact-Induced Oxygen Scavenging in Indium Tin Oxide Transistors Sumaiya Wahid, Mahnaz Islam, Christopher Perez, Timothy D Brown, Michelle E Chen, Matthew A Marcus, Hendrik Ohldag, Suhas Kumar, Eric Pop Semiconducting oxide transistors are promising for several applications due to their ultralow leakage current and compatibility with silicon processing. However, their stability and performance degradation at short channel lengths are often poorly understood. Here, for the first time, we use x-ray absorption spectroscopy to probe oxygen migration in metal-insulator-semiconductor-metal (MISM) test structures, as a cause for the instability of indium tin oxide (ITO) transistors. |
Wednesday, March 8, 2023 3:48PM - 4:00PM |
Q34.00005: Effects of Charge Traps on Electronic Transport in 2D WSe2 Field-Effect Transistors FIDA ALI Atomically thin layer transition metal dichalcogenides (TMDs) are structurally ideal channel materials to design the ultimate atomic electronics after the silicon era. However, the charge transport in atomically thin (monolayer, bilayer, and trilayer) TMDs-based field-effect transistors (FETs) devices are strongly influenced by charge traps originating from an intimate environment. Therefore, to analyze the impact of charge traps on the intrinsic nature of charge transport behavior in different thicknesses WSe2 devices, we performed temperature-dependent electrical transport measurements of different thicknesses WSe2 devices (monolayer to multilayer). Different thicknesses of WSe2-based FETs show different charge transport regimes in the insulating region and metal-insulator transition (MIT) at higher temperatures. The obtained conductivity results suggest the intermediate tunneling-hopping transport coexists in the insulating regime at low temperatures. The hopping parameter To and localized length significantly vary with the thickness of the WSe2 flake, indicating the different disorder landscapes forms with reducing channel thickness. While at high temperatures, the insulating nature of the system changes into metallic, where the conductivity is reduced with increasing temperature. |
Wednesday, March 8, 2023 4:00PM - 4:12PM |
Q34.00006: Image force derivation and application to two-dimensional materials contacts Emeric Deylgat, Sarah R Evans, Edward Chen, Massimo V Fischetti, Bart Soree, William G. Vandenberghe Transistors made from two-dimensional (2D) materials such as transition-metal dichalcogenides (TMDs) are characterized by high contact resistances. To make performant devices, it is important to estimate the contact resistances accurately using suitable models. |
Wednesday, March 8, 2023 4:12PM - 4:24PM |
Q34.00007: Atomic silicon wires: dopant mediated charging characterization Max Yuan, Roshan Achal, Jeremiah Croshaw, Robert A Wolkow, Taras Chutora, Jason Pitters, Lucian Livadaru, Furkan M Altincicek CMOS technologies are approaching their performance limits. Atomic silicon electronics are poised to provide the next-generation of devices. This beyond CMOS platform consists of exactingly patterned dangling bond (DB) circuitry on hydrogen passivated silicon (H-Si).1 Many passive and active components can be made of DBs, here we investigate atomic silicon wires. We employ a recent dopant based charge sensing procedure in conjunction with non-contact atomic force microscopy to study the charging behavior of atomically fabricated DB wires on H-Si (100) 2x1. On its own, this method can be used to rapidly detect local net charge with single electron sensitivity; coupled with AFM, it can drastically improve confidence in data interpretation.2 In this scheme, a single DB sensor is employed to detect a sharp step in its I(V) spectroscopy due to the ionization of a nearby arsenic dopant. As charged DBs are fabricated nearby, local band bending shifts the dopant ionization voltage which can act as a charge sensor. Wires, both parallel and perpendicular to the dimer direction were systematically lengthened and studied using this method. The charging behavior for various lengths of wire, and novel observations, such as a length dependent flip flop in electron occupation for perpendicular wires are demonstrated. This method and these results will be used to improve the characterization of DB structures and will eventually be directly compared to theory to improve the modeling of DB circuitry.
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Wednesday, March 8, 2023 4:24PM - 4:36PM |
Q34.00008: Theory of electron transport in direct-gap Ge1-xSnx group-IV alloys Christopher A Broderick, Sarita Das, Michael D Dunne, Eoin P O'Reilly Incorporation of Sn in Ge to form the Ge1-xSnx alloy has been predicted and experimentally confirmed to drive an indirect- to direct-gap transition [1]. This signals significant potential for applications in electronic and photonic devices compatible with a Si platform, stimulating significant ongoing effort to develop post-CMOS devices [2]. We combine atomistic electronic structure calculations with explicit numerical solution of the Boltzmann transport equation (BTE) to quantify the evolution of electron transport in semiconducting Ge1-xSnx. Using alloy supercell calculations we evaluate intra- and inter-valley alloy scattering rates, demonstrating that Sn-induced hybridization of the direct (Γ6c) and indirect (L6c) conduction band edge states of Ge mediates strong Sn-induced inter-valley scattering. At zero applied electric field, we predict a strong increase in electron mobility as the alloy becomes direct-gap for Sn composition x > 8%. Solution of the BTE in the presence of a driving electric field demonstrates increased sensitivity of the mobility to applied electric field in the direct-gap regime. Finally, we summarize atomistic calculations of the Sn composition dependent alloy band-to-band tunneling rate and its implications for applications in tunneling field-effect transistors. |
Wednesday, March 8, 2023 4:36PM - 4:48PM |
Q34.00009: Reconfigurable Logic Transistors Based on 2D Heterostructures Junzhe Kang, Shaloo Rakheja, Wenjuan Zhu Reconfigurable transistors can enable the design of highly compact logic circuits to realize more complex systems due to their ability to program polarity during run-time. Two-dimensional (2D) atomically thin transition metal dichalcogenides (TMDC) are of particular interest as the channel material for reconfigurable transistors because of their unique gate-tunable electronic properties. Reconfigurable transistors based on ambipolar 2D semiconductors, such as MoTe2, have been previously demonstrated. However, the relatively large bandgap of MoTe2 resulted in insufficient on-state current. Here, we introduce electrostatically reconfigurable transistors based on vertical and lateral TMDC heterostructures. The external vertical electric field in the source/drain contact regions can selectively facilitate one type of carrier injection, hence controlling the polarity of the device. Strong and tunable unipolar conduction was achieved for reconfigurable transistors based on vertical and lateral TMDC heterostructures with two different measurement setups. These reconfigurable logic devices possess the potential to function as critical components for next-generation computing systems. |
Wednesday, March 8, 2023 4:48PM - 5:00PM |
Q34.00010: Field effect two-dimensional electron gases in modulation-doped InSb surface quantum wells Emma A Bergeron We report on transport characteristics of field effect two-dimensional electron gases in surface indium antimonide quantum wells. A 5 nm thin n-InSb capping layer is shown to promote the formation of reliable, low resistance Ohmic contacts to surface InSb quantum wells. High quality single-subband magnetotransport with clear quantized integer quantum Hall plateaus are observed to filling factor ν=1 in magnetic fields of up to B=18 T. We show that the electron density is gate-tunable, reproducible, and stable from pinch-off to 4×1011 cm−2, and peak mobilities exceed 24,000 cm2/Vs. Rashba spin-orbit coupling strengths up to 130 meV⋅Å are obtained through weak anti-localization measurements. An effective mass of 0.019me is determined from temperature-dependent magnetoresistance measurements. By comparing two heterostructures with and without a doping layer beneath the quantum well, we find that the carrier density is stable with time when doping in the ternary AlInSb barrier is not present. Finally, the effect of modulation doping on structural asymmetry between the two heterostructures is characterized. |
Wednesday, March 8, 2023 5:00PM - 5:12PM |
Q34.00011: Temperature and barrier height tunable current mechanism of a reverse-bised graphene-WS2 barristor junction INCHUL CHOI, Nae Bong Jeong, Minjeong KIM, Jaeho Yu, Hyun-Jong Chung In traditional semiconductor physics, the reverse-bias current of the Schottky junction is composed of the thermionic emission (TE) current and the Fowler-Nordheim tunneling (FNT) current; both are regarded as fixed. In this study, we studied the evolution of the reverse-biased current of the graphene-WS2 junction barristor device by varying the barrier height and temperature. It originated from the barristor being a barrier-height-tunable device and temperature varying the doping level of the semiconductor, resulting in the modulation of the barrier thickness. As the barrier height decreases with electrons on graphene, the dominant transport mechanism of the junction changes from TE to FNT. As the temperature increases, the doping concentration of the WS2 increases, and thus the barrier thickness decreases, resulting in the same evolution of the dominant transport. In addition, we observed the kink of the ID-VD curves at a specific range of gate voltage and temperature. It could originate from the alignment of the Fermi level of graphene near the Dirac point, which dramatically reduces the FNT current. |
Wednesday, March 8, 2023 5:12PM - 5:24PM |
Q34.00012: Quasi Van der Waals Epitaxiay of Magnetic Topological Insulator on GaAs (111) Substrate Yuxing Ren, Lixuan Tai, Hung-Yu Yang, Xiang Dong, Ting-Hsun Yang, Yaochen Li, Kang Wang Magnetic topological insulator could achieve quantum anomalous Hall (QAH) effect and spin-orbit torque (SOT) switching in the same structure. This is promising for its future applications in memory or switching applications with its robust surface properties by topological protection. In this work we have grown Cr:(BixSb1-x)2Te3 and MnBi2Te4 on GaAs |
Wednesday, March 8, 2023 5:24PM - 5:36PM |
Q34.00013: The impact of asperity shape and gradient elasticity in flexoelectric/triboelectric contacts Karl P Olson Flexoelectricity, the coupling of strain gradients and polarization, is necessary to explain the charge transfer that occurs when an insulator contacts another material, known as triboelectricity. When asperities at the surface of materials contact, they deform with a large strain gradient, which drives charge transfer via the flexoelectric effect [1]. Previously, we have developed an experimentally verified model for metal-semiconductor contacts which explains the force-dependence of current when an atomic force microscope tip is used to deform the semiconductor [2]. |
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