Bulk loss in silicon substrates for superconducting quantum circuits

Superconducting qubits are a leading candidate for large-scale, fault-tolerant quantum computing. It is critical to understand and minimize losses originating in the materials used to realize the qubit. While loss is generally dominated by two-level state defects in amorphous interfaces, advances in qubit design and materials have led to steady reductions in interface losses over the years. Ultimately, qubit coherence will be limited by bulk losses in the silicon or sapphire substrate, about which surprisingly little is known. Here we describe a novel testbed based on a 3D stub cavity resonator designed to probe bulk loss in candidate qubit substrates. We present the results of numerical simulations that have guided optimization of the 3D cavity resonator. We present a thorough study of bulk loss in silicon grown according to different methods, subjected to different post-growth anneal protocols, and with different crystal orientation.