Session G70: Quantum Circuit Optimization and Transpilation

Quantum Circuit Optimization and Transpilation via Parameterized Circuit Instantiation

Parameterized circuit instantiation is a common technique encountered in the generation of circuits for a large class of hybrid quantum-classical algorithms. Despite being supported by popular quantum compilation infrastructures such as IBM Qiskit and Google Cirq, instantiation has not been extensively considered in the context of circuit compilation and optimization pipelines. In this work, we describe algorithms to apply instantiation during two common compilation steps: circuit optimization and gate-set transpilation. When placed in a compilation workflow, our circuit optimization algorithm produces circuits with an average of 13% fewer gates than other optimizing compilers. Our gate-set transpilation algorithm can target any gate-set, even sets with multiple two-qubit gates, and produces circuits with an average of 12% fewer two-qubit gates than other compilers. Overall, we show how instantiation can be incorporated into a compiler workflow to improve circuit quality and enhance portability, all while maintaining a reasonably low compile time overhead.   

Efficient Quantum Circuit Design with a Standard Cell Approach

We propose a new method for designing quantum circuits which utilizes standard cells similar to those found in classical circuit design. This method can be used prior to deciding to compile to either NISQ or lattice surgery circuits to obtain good resource estimates for a final compiled circuit. Our method relies on the regular structure found in many quantum circuits, and allows for estimation of the resources necessary for the circuit without using complex compilation methods. We demonstrate the effectiveness of our method by first designing standard cells for two Toffoli gate decompositions then using these standard cells to route a quantum multiplier on a 3D architecture with nearest neighbor connectivity. When comparing the SWAP depth and SWAP count of the final circuit with an equivalent circuit routed using automated routing tools available in cirq, we find that our method results in a shallower SWAP-depth (by at least 2.5x) and uses fewer SWAP gates.   

Using Quantum Hardware Speed Limits to Improve Basis Gate Selection

Increasing Quantum Circuit (QC) fidelity requires an efficient co-designed instruction set which minimizes the use of costly gate applications. The choice of a hardware basis gate depends on a QC’s native Hamiltonian interactions among the qubits. However, calibrating gates is an expensive process, so we inspect the Hamiltonian along with quantum algorithms to find which single gate type yields the shortest overall circuit duration, and therefore maximum overall circuit fidelity.  We use gate durations and expected costs from Haar random unitaries to design transpilation passes using numerical decomposition tools. We characterize hardware speed limits in a case study of a SNAIL modulator to find the maximum driving strengths given a gate’s interaction parameters.  Next, we optimize the interleaved 1Q and 2Q gate templates using monodromy polytopes [Peterson, et. Al, Quantum 4 (2020)] and a Hilbert-Schmidt cost function. We also extend our decomposition tool using entropic measures to perform entangled state creation. We will present our recent simulated fidelity improvements using our software tool. Finally, we will also comment on the limitations of gate optimizations because of controlled-unitaries dominating quantum algorithm designs.

    

SimuQ: A Domain-Specific Language For Quantum Simulation With Analog Compilation

Hamiltonian simulation is one of the most promising applications of quantum computing. Recent experimental results suggest that continuous-time analog quantum simulation would be advantageous over the gate-based digital quantum simulation in the NISQ era. However, programming such analog quantum simulators is much more challenging due to the lack of a unified interface between hardware and software and the only few known examples are all hardware-specific. We present SimuQ, the first domain-specific language for Hamiltonian simulation that supports pulse-level compilation to heterogeneous analog quantum simulators. Specifically, in SimuQ, front-end users will specify the target Hamiltonian evolution with a Hamiltonian specification language, and the programmability of analog simulators is specified through a new abstraction called the abstract analog instruction set by hardware providers. Through a solver-based compilation, SimuQ will generate the pulse-level instruction schedule on the target analog simulator for the desired Hamiltonian evolution, which has been demonstrated on pulse-controlled superconducting (Qiskit OpenPulse) and neutral-atom (Bloqade) systems, as well as on normal digital machines. We also show the advantage of the analog compilation over the digital one on IBM machines and the use of SimuQ for resource estimation for hypothetical analog machines.   

A Case for Efficient and Scalable Tree-Based Quantum Circuit Simulator

Quantum computers can speed up computationally hard problems. However, to realize their full potential, we must mitigate qubit errors (from noise) by developing noise-aware algorithms, compilers, and architectures. Thus, simulating quantum programs on classical computers with different noise models is a de-facto tool that is used by researchers and practitioners. Unfortunately, for large quantum circuits, noisy simulators iteratively execute the same circuit across multiple trials (shots) – thereby incurring large performance overheads.

To address this, we propose a noisy simulation technique called Tree-Based Quantum Circuit Simulation (TQSim). TQSim exploits the reusability of the intermediate results during the noisy simulation and reduces computation. TQSim dynamically partitions a circuit into several subcircuits. It then reuses the intermediate results from these subcircuits during computation. As compared to a noisy Qulacs-based baseline simulator, TQSim achieves an average speedup of 2.51× across 48 different benchmark circuits. Additionally, across benchmarks, TQSim produces results with a normalized fidelity that is within 0.016 range of the baseline normalized fidelity. TQSim maintains the same speedup when going from single-node to multi-node simulation   

Ansatz Learning for Quantum Circuit Optimization

The goal of quantum circuit optimization is to reduce the number of operations and the critical path depth of computation in quantum circuits. Techniques such as unitary synthesis and quantum circuit instantiation have proven to be effective methods of optimizing quantum programs. These bottom-up optimization techniques begin with a blank circuit and add gates until the original target circuit or unitary is implemented to within some very small approximation error. The run time of such algorithms typically scale exponentially with the number of qubits or width of the circuits. Much of this run time is dedicated to finding the placement of gates within the circuit. This project explores the use of machine learning in identifying good quantum circuit ans ¨atze for the purposes of quantum circuit optimization.   

Using machine learning for autonomous selection of optimal qubit layouts on quantum devices

In recent years, the experimental performance of quantum algorithms on real hardware has increased substantially. This is due not just to advancements in quantum hardware, but also the development of a vast array of classical preprocessing techniques. Advancements in compilation, layout selection, and quantum control have been used to push the performance of quantum devices right up to the hardware limit. Layout selection is the process by which virtual qubits in a quantum circuit representation are mapped to a subset of physical qubits on a quantum computer. Choosing a suboptimal qubit layout can be very detrimental for the performance of a quantum algorithm. On NISQ-era quantum devices, each qubit often has a unique coherence time, readout error, gate fidelity, and so on. Before executing a circuit, experts need to carefully balance these traits to select an optimal qubit layout, thus hopefully maximising the performance of the device. In this work, we explore the effects of layout selection on quantum algorithm performance. We propose a set of heuristics for performing layout selection on quantum devices. We observe that an optimal layout can increase algorithm success probability up to 3x when compared to a suboptimal layout. Using our methods, we are able to achieve substantial improvements on real hardware across a wide range of quantum algorithms such as BV, QAOA, and QFT. We also demonstrate that our tools vastly outperform existing solutions.   

Interaction graph-based profiling of quantum circuits for algorithm-aware mapping techniques

Quantum circuit mapping techniques are crucial for successfully executing quantum algorithms on current resource-constrained and error-prone quantum processors. They perform some modifications on the quantum circuit so that it complies with the hardware restrictions, while trying to minimize the resulting gate and depth overhead to increase the circuit success rate. Most quantum circuit mapping techniques focus on the hardware properties, though some works have already pointed out the importance of also considering algorithm characteristics. 

We perform thorough profiling of quantum circuits by not only extracting parameters like the number of qubits and gates and two-qubit gate percentage, but also graph theory-based metrics from their corresponding qubit interaction graph (distribution of two-qubit gates among qubits) and gate-dependency graph (relations between gates). In-depth profiling of quantum circuits could be significant to: i) have a deeper understanding of why some circuits have higher fidelity than others when being run on a particular processor using a specific mapping technique and ii) develop application-driven mapping methods.

After clustering the quantum circuits based on the derived parameters and graph metrics, we observe a clear correlation between them and the mapping and circuit performance metrics (i.e gate and latency overhead and fidelity) when considering the constraints of three different superconducting quantum processors.

    

Qubit-reuse compilation with mid-circuit measurement and reset

A number of commercially available quantum computers, such as those based on trapped-ion or superconducting qubits, can now perform mid-circuit measurements and resets. This capability can help reduce the number of qubits needed to execute many types of quantum algorithms by measuring qubits as early as possible, resetting them, and reusing them elsewhere in the circuit. We introduce the idea of qubit-reuse compilation, which takes as input a quantum circuit and produces as output a compiled circuit that requires fewer qubits to execute due to qubit reuse. We present two algorithms for performing qubit-reuse compilation: an exact constraint programming optimization model and a greedy heuristic. We introduce the concept of dual circuits, obtained by exchanging state preparations with measurements and vice versa and reversing time, and show that optimal qubit-reuse compilation requires the same number of qubits to execute a circuit as its dual. We illustrate the performance of these algorithms on a variety of relevant near-term quantum circuits, such as one-dimensional and two-dimensional time-evolution circuits, and numerically benchmark their performance on the quantum adiabatic optimization algorithm (QAOA) applied to the MaxCut problem on random three-regular graphs. To demonstrate the practical benefit of these techniques, we experimentally realize an 80-qubit QAOA MaxCut circuit on the 20-qubit Quantinuum H1-1 trapped ion quantum processor using qubit-reuse compilation algorithms.   

Compilation of Quantum Applications to Hardware Primitives

We present results from compilation software that tailors the execution of quantum applications to underlying hardware primitives. Exemplar techniques employed include native gateset decomposition, echoed noise mitigation, dynamical decoupling, noise-aware mapping, and crosstalk avoidance. In each such technique, the compiler must be made aware of the underlying device physics. We present experimental results from cold atom, superconducting, and trapped ion hardware. On multiple benchmark applications, we observe 10x improvements in performance, with further enhancements possible at larger program sizes.