Optimized Fermionic SWAP Networks Via Hardware-Aware Compilation and Equivalent Circuit Averaging for QAOA*

Hardware-aware compilation techniques and gate-based optimizations play a key role in minimizing errors and maximizing performance of noisy intermediate-scale quantum (NISQ) devices.  The fermionic SWAP network is an important quantum subroutine that can be used to efficiently implement NISQ quantum applications such as the Quantum Approximate Optimization Algorithm (QAOA) on dense graphs with just a minimally-connected qubit topology.  In this work, we present low-level tools which further improve the performance of fermionic SWAP networks: (1) optimized gate decompositions utilizing a richer variety of hardware operations, (2) circuit compilation exploiting the degrees of freedom in each gate decomposition to maximize single-qubit gate cancellation, and (3) Equivalent Circuit Averaging (ECA), a new technique to efficiently mitigate systematic errors by averaging over equivalent circuit decompositions.  These optimizations are experimentally validated on the Advanced Quantum Testbed, where we find a 60% average reduction in total variation distance for depth-1 QAOA circuits executed on four superconducting transmon qubits.