Topology Aware Unitary Synthesis for Scalable Quantum Circuit Optimization*

Unitary synthesis is an optimization technique that can achieve optimal multi-qubit gate counts for many classes of quantum circuits, but is ultimately limited in scalability by its exponential memory requirements. Applying unitary synthesis to large width quantum circuits requires divide-and-conquer partitioning of circuits into smaller components that can be directly optimized. In this talk, we will present features of the scalable synthesis BQSKit toolkit that enable the optimization of circuits with hundreds of qubits. We will examine the tradeoffs for different partitioning techniques and discuss what parameters of partitioned subcircuits most influence synthesis performance. We will additionally explore the impact of physical qubit topology on the multi-qubit gate count of synthesized circuits. Finally, we propose a topology aware synthesis technique that partitions quantum circuits and matches subcircuits with "physical" qubit sub-topologies before optimizing. We will demonstrate how this technique can be used to improve the multi-qubit gate count of large width quantum circuits on realistic physical topologies. When compared with traditional quantum compilers using peephole optimization and mapping algorithms such as Qiskit, Tket or Cirq, our approach is able to provide significant circuit depth reduction with little sensitivity to the underlying physical chip topology.