Design and analysis of superconducting quantum processors for surface code*

We present an effective numerical method to analyze bus-mediated qubit-qubit couplings and two-qubit-gate speed limits in superconducting quantum processors designed for surface-code quantum error correction. Our hybrid simulation tool, combining finite-element and circuit simulation, enables the investigation of a complex chip layout with limited computational resources. We apply the simulation method to the design of Surface-17 and -49 processors, finding good agreement with the experimental realization of Surface-17.