Extensible circuit QED processor architecture with vertical I/O*

Achieving quantum fault tolerance in an extensible architecture is an outstanding challenge across experimental quantum computing platforms today. Traditionally, circuit QED processors have millimeter dimensions and lateral coupling for all input/output (I/O) signals, precluding the increase in qubit numbers beyond \textasciitilde 10. We present a scalable footprint for circuit QED processors with vertically coupled I/O. Our demonstration using centimeter scale chips can accommodate the \textasciitilde 50 qubits needed in next-generation processors targeting the experimental demonstration of quantum fault tolerance.