Session T23: Invited Session: Industrial Physics Forum: Device Physics at the Nanoscale

Spin Transistor, Spin Circuits and Spin Logic

There has been enormous progress in the last two decades effectively combining spintronics and magnetics into a powerful force that is shaping the field of memory devices, but the impact on logic devices still remains uncertain. In light of these developments, this talk will revisit the concept of a spin transistor along with those of spin circuits and spin logic and the theoretical framework used for their analysis and design.   

Nanoscale Magnetic Tunnel Junction

I review state-of-the-art magnetic tunnel junction technology, which is now passing the 20 nm device dimension; the smallest and well characterized reported so far reaching 11 nm [1]. The physics involved in realizing high performance nanoscale magnetic tunnel junction in terms of tunnel magnetoresistance ratio, threshold current for spin-transfer switching, and thermal stability as well as the materials science involved in the technology will be addressed. To simultaneously meet multiple requirements for applications further control and design of materials at the nanometer scale are required. I will discuss about the challenges and future prospects.\\[4pt] [1] H. Sato et al. IEDM 2013.   

Benchmarking emerging logic devices

As complementary metal-oxide-semiconductor field-effect transistors (CMOS FET) are being scaled to ever smaller sizes by the semiconductor industry, the demand is growing for emerging logic devices to supplement CMOS in various special functions. Research directions and concepts of such devices are overviewed. They include tunneling, graphene based, spintronic devices etc. The methodology to estimate future performance of emerging (beyond CMOS) devices and simple logic circuits based on them is explained. Results of benchmarking are used to identify more promising concepts and to map pathways for improvement of beyond CMOS computing.   

Mechanical Computing Redux: Limitations at the Nanoscale

Technology solutions for overcoming the energy efficiency limits of nanoscale complementary metal oxide semiconductor (CMOS) technology ultimately will be needed in order to address the growing issue of integrated-circuit chip power density. Off-state leakage current sets a fundamental lower limit in energy per operation for any voltage-level-based digital logic implemented with transistors (CMOS and beyond), which leads to practical limits for device density (i.e. cost) and operating frequency (i.e. system performance). Mechanical switches have zero off-state leakag and hence can overcome this fundamental limit. Contact adhesive force sets a lower limit for the switching energy of a mechanical switch, however, and also directly impacts its performance. This paper will review recent progress toward the development of nano-electro-mechanical relay technology and discuss remaining challenges for realizing the promise of mechanical computing for ultra-low-power computing.   

Many-Body Switches

Most current electronic devices use gate voltages to switch individual electron transport channels or off. This architecture necessarily leads to operating voltages that are much larger than the temperature thermal energy, and places lower bounds on power consumption that are becoming. I will discuss strategies for achieving devices in which gates are used to collective many-electron states, in principle allowing charge transport to be switched by smaller voltage changes and both operating voltages and power consumption to reduced. I will specifically address devices based on the properties of itinerant electroninsulating magnetic systems, and devices based on bilayer exciton condensation. This work is based on work performed in collaboration with Sanjay Banerjee and Frank Register.