Session V20: Invited Session: High k Dielectrics for High Carrier Mobility Channel Applications

Materials and Device Aspects of III-V 3D Transistors

Recently, III-V MOSFETs with high drain currents (I$_{ds}>$1mA/$\mu $m) and high transconductances (g$_{m}>$1mS/$\mu $m) have been achieved at sub-micron channel lengths (L$_{ch})$, thanks to the better understanding and significant improvement in high-k/III-V interfaces. However, to realize a III-V FET at beyond 14nm technology node, one major challenge is how to effectively control the short channel effects (SCE). Due to the higher permittivity and lower bandgap of the channel materials, III-V MOSFETs are more susceptible to SCE than its Si counterpart. The scaling of planar devices stops at around 150nm L$_{ch}$. The dramatic increase in DIBL beyond 150nm indicates severe impact from 2D electrostatics. Therefore, the introduction of 3-dimensonal (3D) structures to the fabrication of sub-100nm III-V FETs is necessary. In this talk, we will review the materials and device aspects of III-V 3D transistors developed very recently [1-3]. \\[4pt] [1] Y. Q. Wu \textit{et al}. IEDM Tech. Dig. 331 (2009).\\[0pt] [2] M. Radosavljevic \textit{et al.}, IEDM Tech. Dig. 126 (2010).\\[0pt] [3] J. J. Gu \textit{et al}. IEDM Tech Dig. 2011 (in press).   

Pushing the material limit and physics novelty in high $\kappa$'s/high carrier mobility semiconductors for post Si CMOS

The semiconductor industry is now facing unprecedented materials/physics challenges due to the scaling-limitation of Si CMOS transistor arising from non-scaling of matters, namely gate dielectrics and channel mobility. The new technology using high-$\kappa $ plus metal gate on high carrier mobility semiconductors of InGaAs and Ge will lead to faster speed at lower power. The tasks for realizing the new devices equivalent oxide thickness (EOT) $<$ 1 nm, interfacial density of state (D$_{it}) \quad \le $ 10$^{11}$ eV$^{-1}$cm$^{-2}$, self-aligned process, low parasitic, and integration with Si, have been solved or are being feverishly studied. The key of achieving the above goals is to understand/tailor interfaces of the high $\kappa $'s/InGaAs (Ge). Tremendous progress has been made using molecular beam epitaxy (MBE) and atomic layer deposition (ALD) high $\kappa $'s of Ga$_{2}$O$_{3}$(Gd$_{2}$O$_{3})$, Al$_{2}$O$_{3}$, and HfO$_{2}$, and the novel ALD/MBE dual dielectrics in attaining an EOT of 0.5 nm, D$_{it}$ of low 10$^{11}$ eV$^{-1}$cm$^{-2 }$(with a flat D$_{it}$ distribution versus energy), and thermal stability at high temperatures higher than 800\r{ }C of the MOS structures. Electronic/electrical characteristics of the hetero-structures have been studied using in-situ synchrotron radiation photo-emission, cross-sectional scanning tunneling spectroscopy, capacitance (conductance)-voltage under various temperatures, and charge pumping methods. Device performance in world-record drain currents, transconductances, sub-threshold swings, etc. in self-aligned inversion-channel high $\kappa $'s/InGaAs and /Ge MOSFET's will also be presented. This work has been supported by Nano National Program (NSC 100-2120-M-007-010) of the NSC of Taiwan, and the AOARD of the US Air Force. \\[4pt] In collaboration with J. Kwo, W. C. Lee, M. L. Huang, T. D. Lin, Y. C. Chang, Y. H. Chang, C. A. Lin, Y. M. Chang (NTHU and NTU in Taiwan), T. W. Pi, C. H. Hsu (NSRRC in Taiwan), Y. P. Chiu (NSYSU in Taiwan), C. Merckling (IMEC in Belgium), J. I. Chyi (NCU, Taiwan), and G. J. Brown (AFRL, USA).   

Bonding principles of the Passivation Mechanism at III-V -- oxide Interfaces

It has always been much more difficult to make FETs from GaAs than Si, because of `Fermi level pinning' and the difficulty of passivating its surfaces and interfaces. These issues have been discussed from the early days of PCSI by Spicer et al [1] with their ``unified defect model.'' Hasegawa [2] introduced the idea of ``Disorder Induced Gap states'' (DIGS). Since 1997 it has been possible to make inverted MOSFETs on GaAs using the epitaxial Gadolinium gallium oxide [3], but the main impetuous has been since 2003 to use atomic layer dpeosition to make scalable FETs, as recently acheived by Intel [4]. The obvious question is why GaAs is so much more difficult to passivate than Si. The early answer was that the native oxide was poor. But since the advent of good deposited ALD oxides on Si such as HfO2 or Al2O3, this answer is no good, as they should also work on GaAs. They do to an extent, but the interfacial density of states is still too large and the CV p~lots are distorted. The cause of the defects is cannot be due to stress. The reason must be some underlying chemical reason. I show that the reason is the polar nature of bonding in GaAa and other III-Vs, and the driving force to keep the Fermi level in a gap. The electron counting rule of Pashley [5] that describes surface reconstruction is shown to be a variant of auto-compensation, and it is proposed to work more generally, at each layer deposition or growth on GaAs [6]. This leads to a continuous generation of defects if it is not satisfied. So the answer is to deposit oxide layers that meet this rule, and also break up any surface reconstructions that would lead to As-As dimers [6]. \\[4pt] [1] W E Spicer, Phys Rev Lett \textbf{44} 420 (1980)\\[0pt] [2] H Hasegawa, J Vac Sci Technol B 5 1097 (1987)\\[0pt] [3] M Hong et al, Science \textbf{283} 1897 (1997)\\[0pt] [4] M Radosavljevic, et al, IEDM (2009) p13.1\\[0pt] [5] M D Pashley, Phys Rev B \textbf{40} 10481 (1989)\\[0pt] [6] J Robertson, L Lin, App Phys Letts (submitted), App Phys Lett \textbf{98} 082903 (2011)   

Exploring Ge and III-V devices to scale CMOS beyond the Si roadmap

There is lots of interest in the use of germanium and III-V compounds as channel material in future CMOS generations. Direct growth of Ge and III-V in Si trenches allows to co-integrate these materials on bulk Si substrates. The formation of antiphase domain boundaries during epitaxy of III-V materials can be avoided by creating double atomic steps at the bottom of the trench through controlled Ge surface profiling. Much effort was dedicated to the electrical passivation of the interface between the high-k dielectric and these materials. Despite its relatively poor stability GeO2-like passivation of Ge has been demonstrated for both pMOS and nMOS devices. Si capping layers of only a few monolayers were used to fabricate short channel Ge pMOS devices with high drive currents. Other successful Ge passivation methods are based on surface treatments such as in situ H2S or wet (NH4)2S. Devices in III-V materials often suffer from Fermi level pinning associated with a high density of defect states near the high-k/III-V interface. These defects can be suppressed by optimized (in-situ) surface treatments and precise control of the oxidation states at the high-k/III-V interface. The Al2O3/ InGaAs interface has been extensively investigated, often concentrating on the possibility to remove Ga and As oxides by exposure to trimethylaluminum (TMA) during atomic layer deposition (ALD), but good passivation has also been demonstrated with various other high-k materials. Since most III-V materials have a low conduction band density of states, the surface potential travels far into the conduction band before the necessary amount of mobile charge is accumulated at the interface. Therefore, the defect density at these energy levels must also be reduced, including border traps in the high-k layer that cause frequency dispersion in the capacitance-voltage behaviour. Finally, it is noteworthy to mention that the introduction of these advanced materials also allows the development of new device concepts, such as Implant-Free Quantum Well devices, heterojunction TunnelFETs and nanowire devices, that can fully exploit the properties of these new materials.