Session Q28: Focus Session: Carbon Nanotubes and Related Materials: Devices II

Carbon nanotube based NEMS actuators and sensors

Single-walled carbon nanotubes (SWNTs) have been widely studied due to superior mechanical and electrical properties. We have grown vertically aligned SWNTs (VA-SWNTs) onto microcantilever (MC) arrays, which provides an architecture for novel actuators and sensors. Raman spectroscopy confirms that the CVD-grown nanotubes are SWNTs and SEM confirms aligned growth. As an actuator, this hybrid MC/VA-SWNT system can be electrostatically modulated. SWNTs are excellent electron acceptors, so we can charge up the VA-SWNT array by applying a voltage. The electrostatic repulsion among the charged SWNTs provides a surface stress that induces MC deflection. Simulation results show that a few electrons per SWNT are needed for measureable deflections, and experimental actuators are being characterized by SEM, Raman, and an AFM optical lever system. The applied voltage is sinusoidally modulated, and deflection is measured with a lock-in amplifier. These actuators could be used for nano-manipulation, release of drugs from a capsule, or nano-valves. As a sensor, this MC/VA-SWNT system offers an improved sensitivity for chemical and bio-sensing compared to surface functionalized MC-based sensors. Those sensors only have a 2D sensing surface, but a MC/VA-SWNT system has significantly more sensing surface because the VA-SWNTs extend microns off the MC surface.   

High yield assembly and electron transport investigation of semiconducting-rich local-gated single-walled carbon nanotube field effect transistors

Single-walled carbon nanotubes (SWNTs) are ideal for use in nanoelectronic devices because of their high current density, mobility and subthreshold slope. Using individual local gates and scaling the gate oxide has shown faster switching behavior and lower power consumption. However, assembly methods must be developed to reproducibly align all-semiconducting SWNTs at specific locations with individually addressable gates for future integrated circuits. We show high yield assembly of local-gated semiconducting SWNTs assembled via AC-dielectrophoresis (DEP). Detailed electron transport investigations on the devices show that 98{\%} display good FET behavior, with an average threshold voltage of 1V and subthreshold swing as low as 120 mV/dec.   

Measurement of quantum capacitance in individual semiconducting single-walled

The capacitance of a carbon nanotube consists of its geometrical capacitance and its quantum capacitance. The latter is determined by the electronic density of states of the nanotube and the electron interactions, therefore it is a tool for probing fundamental electronic properties in carbon nanotubes, as well as an important parameter to design carbon nanotube electronic devices. The quantum capacitance of a carbon nanotube was first measured by using a capacitance bridge at 77K [1]. Here we extract the quantum capacitance of a semiconducting single-walled carbon nanotube in two one-dimensional subbands from electronic transport measurements at 4.2 K. We compare our results to other experiments and predictions from theoretical models.\\[4pt] [1] S. Ilani, L. A. K. Donev, M. Kindermann, and P. L. McEuen, Nature Physics, 2, 687, (2006).   

Electronic transport in intermediate sized carbon nanotubes

We have measured low temperature transport properties of multiwalled carbon nanotubes (MWNT) of different diameters in the range 2-10 nm [1]. In nearly all samples the gate dependent conductance exhibits a gap whose size increases with decreasing tube diameter and increasing electrode separation. This so called transport gap is attributed, based on the experimental findings, on a combination of localization effects and narrow diameter induced gaps in the electronic band structure. \\[4pt] [1] M. Ahlskog, O. Herranen, A. Johansson, J. Lepp\"{a}niemi, and D. Mtsuko, Phys. Rev. B \textbf{79}, 155408 (2009).   

Resistance of individual long suspended carbon nanotubes with known atomic structures

We present electrical transport measurement on long individually suspended carbon nanotubes. Single walled carbon nanotubes (SWNTs) are grown by a chemical vapor deposition method across a slit made on silicon oxide/silicon substrate with pre-patterned platinum electrodes. Rayleigh spectroscopy allows us to determine atomic structure indices of individual SWNTs that connect the electrodes across the slit. We investigate the temperature dependent resistance of metallic SWNTs. The relation between electron-phonon interaction in SWNTs in the connection of the atomic structure will be discussed.   

Electrical Resistance of Double-Wall Carbon Nanotubes with Determined Chiral Indices

The properties of carbon nanotubes (CNT), especially single-wall nanotubes (SWNT) and double-wall nanotubes (DWNT), are profoundly sensitive to the atomic structure described by its chirality. CNTs connected to sub-micron electrodes were suspended for transmission electron microscope (TEM) study. We determined the chiral indices of each individual CNT via its nano beam electron diffraction patterns and measured its electrical resistance by the four-probe method at room temperature. We studied the factor of different combinations of semiconducting/metallic shells on the electrical characterizations of DWNTs. The electrical properties were compared between DWNTs and SWNTs and the result show that the electrical transport of a DWNT is dominated by the chiral indices of outer shell.   

Carbon nanotubes for interconnects in integrated circuits

Carbon nanotubes are one of the materials that may be used for advanced interconnects beyond the 16nm node thanks to there extreme resistance to electro migration and to bottom up approach which allow to grow them in tiny holes with very high aspect ratio. The resistance of a via with area A and height h filled with CNT is expressed by $R_{via} =\frac{rq+rsh+rc}{Ad_t }$ where rq, rs, rc are respectively the 6.5k$\Omega $ quantum resistance, the scattering resistance and the contact resistances of one tube. To be competitive with copper via resistance, a large density d$_{t}$ of carbon walls have to be paralleled. Following ITRS needs a density of 2 or 3 10$^{13 }$cm$^{-2}$ conducting CNT walls have to be obtained. This optimum wall density requests the growth of highly packed few nanometre diameter CNTs. Such density has been the main bottleneck for the development of CNT interconnects. Recently ultra high density integration scheme have been demonstrated and for the first time wall density close to the requested one have been integrated in devices. Such density comes from the development on conductive substrates of a CNT growth mode normally used to obtain forests of small tube diameter on insulating substrate like alumina. With this mode, CNTs are grown with base growth mode which is the mode requested for SWCNT or DWCNT thus by continuity it will be possible to increase the density still further by increasing the density of catalyst particles. Our bottom metal of choice is AlCu with iron as catalyst. With this system tube contact resistance between 10$^{4}$ to 10$^{6}$ Ohm have been measured on blanket AlCu substrates. This resistance must be decreased by one or two order of magnitude while increasing further CNT density. In this paper we will present our last integration developments and the role of plasma pre-treatment of the iron aluminium interface in order to decrease the contact resistance. We will show that the bottom profile of via has a major impact on the quality of CNT growing in the holes and discuss future evolutions of this technology.   

Wide Contact Structures for Low-noise Nano-channel Devices based on Carbon Nanotube Network

We developed a wide-contact structure for low-noise devices based on carbon nanotube (CNT) networks. This wide-contact CNT network-based device has a dumbbell-shaped channel which is comprised of a narrow channel region and wide CNT/electrode contact regions. We showed that the wide-contact structure reduced 1/f noise which originated from CNT/electrode contact regions. We also systematically analyzed the noise characteristics of the structured CNT networks and established an empirical formula that can describe the noise behavior of CNT network-based devices including the effect of contact regions and CNT alignment. Interestingly, our noise analysis revealed that the noise amplitude of aligned CNT networks behaves quite differently compared with that of randomly-oriented CNT networks. These results would be an important guideline in designing low-noise nanoscale devices based on CNT networks for various applications such as a highly sensitive low-noise sensor.   

Physics of aligned arrays of single-walled NTs: From transistor to diode applications

NTs have been originally proposed as a 1D high mobility semiconductor material for field-effect transistors (FET). This format is though appeared to be less practical due to low values of the currents through a single NT channel. On contrary, NT massive parallel arrays have already found implementation in flexible and RF electronics. Can we think of NT arrays being another semiconductor thin film materials? Where does the conventional knowledge apply for NT parallel array devices? This talk discusses specialized aspects of physics of electronic and optoelectronic device prototypes and presents recent results for NT FETs and LEDs (light-emitting diode) in parallel array geometries. Cross-talk between individual NTs in the array allows to beat the statistical ``noise'' in the device properties which appears due to randomized NT distribution in the array. Although, taking this into account, device-level characteristics should be used with a care to extract a single NT physical parameters.   

Macroelectronic Integrated Circuits Using High-Performance Separated Carbon Nanotube Thin-Film Transistors

Macroelectronic integrated circuits are widely used in applications such as flat panel display, transparent electronics, as well as flexible and stretchable electronics. However, the challenge is to find the channel material that can simultaneously offer low temperature processing, high mobility, transparency and flexibility. Here in this paper, we report the application of high-performance separated nanotube thin-film transistors (TFTs) for macroelectronic integrated circuits. We have systematically investigated the performance of TFTs using separated nanotubes with 95{\%} and 98{\%} semiconducting nanotubes, and high mobility transistors have been achieved. In addition, we observed that while 95{\%} semiconducting nanotubes are ideal for applications requiring high mobility (up to 67 cm$^{2}$V$^{-1}$s$^{-1})$ such as analog and radio-frequency applications, 98{\%} semiconducting nanotubes are ideal for applications requiring high on/off ratios ($>$10$^{4}$ with channel length down to 4 $\mu $m). Furthermore, integrated logic gates such as inverter, NAND and NOR have been designed and demonstrated using 98{\%} semiconducting nanotube devices, and symmetric input/output behaviour is achieved, which is crucial for the cascading of multiple stages of logic blocks and larger scale integration. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.   

Anisotropic electronic transport in highly aligned carbon nanotube films

Electronic transport in carbon nanotube (CNT) networks has recently attracted much renewed interest due to the numerous advancements in controlling, sorting, and aligning CNTs. Understanding the roles of intra-tube and inter-tube transport in these systems is fundamentally important both from basic and applied points of view. We have studied samples of ultra-long and highly-aligned CNTs grown by CVD and laid down on Si/SiO2 substrates. We designed and fabricated a novel device structure in which we can separately study intra-tube and inter-tube transport. In the intra-tube configuration, ends of ultra-long CNTs were contacted and the current parallel to the alignment direction was measured, whereas, in the inter-tube configuration, transport perpendicular to the alignment direction was probed. We studied the magnetic field and temperature dependence of the resistance between 0.3 K and 300 K, revealing an interesting evolution of transport regimes as for the localization of charge carriers. Preliminary results of photoconductivity measurements will also be presented.   

Air-Stable Conversion of Separated Carbon Nanotube Thin-Film Transistors from P-type to N-type Using Atomic Layer Deposition of High-$\kappa $ Oxide and Its Application in CMOS Logic Circuits

Pre-separated, high purity semiconducting carbon nanotubes hold great potential for thin-film transistors (TFTs) and integrated circuit applications. One of the main challenges it still faces is the fabrication of air-stable N-type nanotube TFTs with industry compatible techniques. Here in this paper, we report a novel and highly reliable method of converting the P-type TFTs using pre-separated semiconducting nanotubes into air-stable N-type transistors by adding a high-$\kappa $ oxide passivation layer using atomic layer deposition (ALD). The N-type devices exhibit symmetric electrical performance compared with the P-type devices in terms of on-current, on/off ratio and mobility. Various factors affecting the conversion process including ALD temperature, metal contact material, channel length, have also been systematically studied. A complementary metal-oxide-semiconductor (CMOS) inverter with rail-to-rail output, symmetric input/output behavior and large noise margin has been further demonstrated. The excellent performance gives us the feasibility of cascading multiple stages of logic blocks and larger scale integration. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.