Session Y38: Focus Session: Emerging Research Devices and Materials for the Microelectronics Industry III

High Mobility InSb Quantum Well with Dislocation Filtering Buffer Layer Grown on GaAs (001) Substrates

A small electron mass makes InSb quantum wells (QWs) with Al$_{x}$In$_{1-x}$Sb barriers attractive for field-effect transistors, mesoscopic magnetoresistors, and ballistic transport devices. The large spin-orbit effects in InSb make InSb QW structures attractive for spin transport devices. The electron mobility of an InSb QW with an Al$_{x}$In$_{1-x}$Sb buffer layer is partly limited by scattering caused by crystalline defects that arise from the large lattice mismatch (14.6{\%}) between the epilayers and the GaAs (001) substrate. Our transmission electron microscopy measurements show that Al$_{x}$In$_{1-x}$Sb/Al$_{y}$In$_{1-y}$Sb interfaces reduce the concentration of threading dislocations. We observed electron mobilities of 38,000 cm$^{2}$/Vs and 121,000 cm$^{2}$/Vs at 300K and 77K, respectively, in an InSb QW grown on a 1.5$\mu $m thick Al$_{x}$In$_{1-x}$Sb buffer layer with two Al$_{y}$In$_{1-y}$Sb interlayers. These values are 16{\%} and 75{\%} higher at 300K and 77K, respectively, than observed in a structure without interlayers. The improved mobility is apparent in studies of geometrical magnetoresistance in devices with channels that are short and wide.   

Large-Scale Array of Pristine Carbon Nanotube Transistors

1D nanostructures such as carbon nanotubes (CNTs) have attracted tremendous attention due to their possible applications including transistors, chemical or biological sensor, etc. However, a lack of a massive manufacturing method for such devices has been an obstacle to their practical applications. Herein, we report a strategy for large scale assembly of CNT-based devices. In this strategy, inert molecular patterns were used to guide the adsorption of CNTs onto bare surfaces to form large scale integrated devices. Using this method, we demonstrated the wafer-scale fabrication of devices based on single-, double-, or multi- walled CNTs on virtually general substrates including SiO$_{2}$, Si, Al, Au, etc. Moreover, we also performed extensive analysis regarding the uniformity of fabricated CNT devices and the yield of this method. Importantly, since our method relies only on conventional semiconductor processing facilities, it is readily accessible for current semiconductor industry and should open up immediate applications such as sensors, FETs, and interconnectors.   

Photocurrent Measurements of Carbon Nanotube PN Junctions

Gated p-n junctions in semiconducting nanotubes have recently drawn much attention for their electronic and optoelectronic characteristics [1,2,3]. We investigate the photocurrent response at a nanotube gated p-n junction using a focused laser illumination source. We find that the photocurrent at zero source-drain bias increases linearly with optical power for the component of light along the length of the nanotube. Scanned photocurrent imaging demonstrates that carrier generation occurs primarily between the p- and n- type segments of the device. Measurements in an optical cryostat down to 4K reveal large photoresponse and step-like structure in the reverse bias photocurrent. These results show that nanotube p-n junctions are highly sensitive, nanoscale photodetectors. [1] J.U. Lee et al, App. Phys. Lett. \textbf{85}, 145 (2004). [2] J.U. Lee, App. Phys. Lett. \textbf{87}, 073101 (2005). [3] K. Bosnick et al, App. Phys. Lett. \textbf{89}, 163121 (2006).   

Carbon nanotube and oxide nanobelt FETs: fabrication, characterization and applications

High-performance field effect transistors (FETs) based on single-wall carbon nanotubes (SWNTs) and oxide nanobelts were fabricated and characterized. The SWNT-FETs were constructed via molecular template-directed assembly of HiPCO tubes onto pre-patterned metal electrodes on a Si/SiO$_{2}$ substrate. The devices exhibit operating characteristics comparable to state-of-the-art CNT FETs, and the process is amenable to large-scale functional CNT circuit assembly. Importantly, the integration of hydrophobic self-assembled organic monolayers in the device structure eliminates the primary source of gating hysteresis in SWNT-FETs, which leads to hysteresis-free FET operation while exposing unmodified nanotube surfaces to ambient air$^{[1]}$. Individual oxide (SnO$_{2}$ and ZnO) nanobelt FETs with multi-terminal contacts were fabricated via conventional lithography. Simultaneous two-terminal and four-terminal measurements enabled direct correlation of the FET characteristics with the nature of the contacts. Low-resistance ohmic contacts on the nanobelts result in high-performance n-channel depletion mode FETs with well-defined linear and saturation regimes, and ``on/off'' ratio as high as 10$^{7}$ at ambient conditions$^{[2]}$. Intrinsic values of the carrier concentration and effective mobility for the nanobelts were consequently obtained. Channel-limited SnO$_{2}$ nanobelt devices show significant modification of the FET characteristics when exposed to gas flows containing 0.2-2{\%} H$_{2}$ at room temperature. The gas sensitivity and response were carefully evaluated$^{[3]}$. The effort to utilize the channel-limited nanobelt FETs for protein detection will be discussed. $^{[1] }$S.A. McGill et al., APL \textbf{89}, 163123 (2006). $^{[2] }$Y. Cheng et al., APL \textbf{89}, 093114 (2006). $^{[3] }$L.L. Fields et al., APL \textbf{88}, 263102 (2006).   

Self-assembly of Epitaxial Monolayers for Vacuum Wafer Bonding.

Self-assembled epitaxial metal monolayers can be used for hetero-integration of mismatched semiconductors, leading to simultaneously low interfacial resistance and high optical transparency. Lattice-mismatched wafers of Si(100) and Si(111) were bonded at room temperature in situ after vacuum deposition of a single atomic layer of Ag on them. The interfacial resistance was measured to be 3.9$\times$ 10$^{-4}$ ohm$\cdot$ cm$^ {2}$ and the optical transmission of the interface at 2500 nm is approximately 98\%. We discuss the important role of electron confinement in ultrathin Ag layers as a possible contributor to the bonding energy.   

Identifying Read/Write Speeds for Field-Induced Interfacial Resistive Switching.

Efforts continue to explore new phenomena that may allow for next generation nonvolatile memory technology. Much attention has been drawn to the field-induced resistive switch occurring at the interface between a metal electrode and perovskite oxide. The switch between high (off) and low (on) resistance states is controlled by the polarity of applied voltage pulsing. Characterization of Ag-Pr$_{0.7}$Ca$_{0.3}$MnO$_{3}$ interfaces via impedance spectroscopy shows that the resistances above 10$^{6}$ Hz are the same at the on and off states, which limits the reading speed to far slower than the applied switching pulses, or device write speed at the order of 10$^{7}$ Hz. We deduce that the switching interface is percolative in nature and that small local rearrangement of defect structures may play a major role.   

Evidence for segregation of Te in ``phase-change" thin chalcogenide Ge-Sb-Te films

The novel chalcogenide phase-change materials are promising candidates for new technologies such as nonvolatile memories and programmable switches in 3D integration and planar logic. They are typically thin Ge-Sb-Te (GST) films, where a thermally induced amorphous-to-crystalline phase transformation can be fast and reversible, with the corresponding large swing in resistance values between the two stable structural states. Here we report on the structural evolution of GST films during thermal cycling and demonstrate using high-resolution (0.5~nm focused probe STEM) scans that Te segregates to the grain boundaries at fairly low temperatures. We show that diffusion of Te along grain boundaries results in its pileup at the free surface and interaction with Ti in adhesion layers in device- compatible stacks. This is consistent with impeded grain growth and with post-crystallization stress release. This motion may impact the ultimate life-cycle of phase-change based devices and should guide the optimal GST material design.   

Characterizing oxide surfaces for successful interfacial resistive switching

Resistive switching has been observed in many oxide-metal interfaces upon application of electric pulses. However, the mechanisms behind the phenomenon and the conditions for obtaining a successful switch are still matters of debate. It has been suggested that local defect rearrangement plays a role in the switching, which suggests that a defect-rich interface is required. There has also been indication that the local application of an electric field greater than some threshold is enough to induce a switch. We attempt to differentiate between these two scenarios by measuring samples with different surface treatments using a needle electrode method. Ac measurements have also been made to characterize the difference between switching and non-switching samples. The results suggest that the switching interface is a percolative layer.   

Band alignments and electron transport in metal/epi-Sc$_{2}$O$_{3}$/Si (111) structures studied by BEEM and Internal Photoemission

Recently, Internal Photemission (Int-PE) has been used to study band alignments between Si and amorphous rare-earth/transition metal oxide films, of interest as possible high dielectric gate insulators for future MOS electronic devices [1,2]. Surprisingly, a variety of these oxide films were found to have nearly the same band alignments and band gap, and also ``tailing'' conduction band (CB) states extending $\sim $1 eV below the primary CB. We have applied Ballistic Electron Emission Microscopy (BEEM) and Int-PE to 20 nm-thick epitaxial Sc$_{2}$O$_{3}$ film grown at 700 $^{o}$C on Si(111), to study electron transport through these ``tail'' states and to estimate oxide fixed charge. These tail states are found to form a ``robust'' CB that supports elastic electron transport even against an applied electric field, with a $\sim $1.1 eV CB offset at the Si interface. Al/epi-Sc$_{2}$O$_{3}$/Si structures were $\sim $1000 times leakier than those made with Pt, consistent with the lower electron tunneling barrier expected for the lower work function Al. The measured dependence of the BEEM threshold voltage on metal bias suggests $\sim $0.2 C/cm$^{3}$ fixed negative oxide charge with a 250 $^{o}$C anneal before Pt deposition and no post-metallization anneal. Work supported by SRC. [1] V. V. Afanas'ev\textit{ et al}., Appl. Phys. Lett. \textbf{85}, 5917 (2004). [2] V. V. Afanas'ev\textit{ et al}., Appl. Phys. Lett. \textbf{88}, 032104 (2006).   

First Principles Study of Strain Effects on the Electronic Properties in Silicon Nanowires

Silicon nanowires have drawn much attention in the past decades due to their potential applications in many fields, such as optoelectronics, micro- and nano- electronics. The study of size dependence on the band gap of silicon wires have been addressed both using theoretical methods and experimental techniques. In parallel, industry routinely applies strain to engineer the electronic properties in bulk Si. In present work, using first principles density functional theory we have studied the uniaxial strain effects on the electronic properties in Si nanowires with lateral dimension up to 5 nm. We discovered that the strain effects on the band gap display qualitatively new trends for the nanowires smaller than $\sim $5 nm. In Si bulk, indirect band gap decreases linearly with hydrostatic compression, while the band gap is increasing with uniaxial compressive strain for wires smaller than 2 nm. In the intermediate size range 2$\sim $5 nm, the band gap decreases both with compressive and tensile strains, exhibiting an approximately parabolic behavior. Finally we will present our results of strain effect on the effective masses of electrons and holes in nanowires that may have immense impact on future nanoelectronics devices.   

Theoretical study of the insulator/insulator interface: band alignment at the SiO$_{2}$/HfO$_{2}$ junction

Hafnia has emerged as a front runner for replacing silica as a gate oxide in CMOS technology. One of the problems which still remains outstanding is finding a p-type gate metal for hafnia. Thus the problem of band alignment at the hafnia/metal and hafnia/Si interfaces has recently received significant attention. However, it is worth noting that during the deposition of hafnia on a silicon substrate a thin layer of silica is always created. And the band alignment between silica and hafnia can dramatically change the overall alignment across the gate stack. In this presentation we will discuss the band alignment at the SiO$_{2}$/HfO$_{2}$ interface. As we shall show it can be significantly different from the simple Schotky limit. We perform \textit{ab-initio s}tudies of the interface using density functional theory in the local density approximation. We construct several atomic level models of the interface which connect hafnia to silica \textit{via} an oxygen plane as required by the electron count rule that ensures the absence of electronic states in the gap. The models differ by the interfacial oxygen coordination, HfO$_{2}$ phases, and strain, and are fully relaxed. All interfaces can be categorized by the interfacial oxygen average coordination number. The calculated valence band offset varies from 1.0 eV to -2.0 eV and most strongly depends on the average coordination of the interface oxygen.   

Extremely Broadband Semiconductor Optical Amplifiers

Extremely broadband InGaAsP/InP ridge bent-waveguide semiconductor optical amplifiers with seven non-identical multiple quantum wells were designed and fabricated on InP substrate. The emission spectra of bent-waveguide semiconductor optical amplifiers at different injection current levels were experimentally studied. To achieve the broadband characteristics, a sequence of non-identical multiple quantum wells were designed. When designing a broadband semiconductor optical amplifier using a non-identical MQW structure, factors such as QW transition energy, number and sequence of different QWs, the thickness of the separate confinement heterostructure layer, the selection of the dominant carrier, the ability of the QW to trap the 2D carrier, the uniformity of the 2D carrier within the QWs, etc. must be taken into account. Using appropriate non-identical MQW structure of SOA allows us to achieve broad emission of semiconductor optical amplifiers. The bandwidth of these semiconductor optical amplifiers is 400 nm, which cover from 1250 to 1650 nm, the range for low-loss window of optical fibers.   

Interband Cascade Laser ($\lambda $ = 3.7 $\mu $m) Operating cw to Thermoelectric Cooler Range

In the mid-infrared, a significant range of wavelengths, from 3.1 to 3.8 $\mu $m, is currently inaccessible to cw semiconductor lasers operating at ambient temperature. The most promising device design for reaching this range is the interband cascade laser (ICL), based on a type-II ``W'' quantum well active region. Here we present results of ICLs fabricated in narrow ridges, which improves both the lateral heat dissipation and the beam quality compared with broad-area lasers. For example, a five-stage ICL with 12-$\mu $m ridge width and Au electroplating for improved epitaxial-side-up heat sinking operates cw to a maximum temperature of 257 K, where the emission wavelength is 3.7 $\mu $m. The device emits 100 mW per facet for cw operation at 80 K, 54 mW at 200 K, and 10 mW at 250 K. The beam quality is within twice the diffraction limit for injection currents up to 14 times the lasing threshold.